📄 init_hdlc.asm
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;********************************************************************************
;* *
;*----------------北京高阳迪威科技有限公司深圳研究中心 -------------------------*
;* *
;* 工程: ASB板测试程序 *
;* 版本: V1.0 *
;* *
;* 作者: LIN QIU FU *
;* 日期: 2001/6/8 *
;* *
;********************************************************************************
;*
;* 文件描述:
;* 通用型子函数
;*
;* 初始化sab82525
;*
;*******************************************************
;
;
.mmregs
;
; 包含文件:
.include "main.inc"
; 引用符号列表:
; 被引用符号列表
.def init_sab82525
; 代码:
.text
;初始化sab82525
;**************************************************************
;*****************the initialization of SAB82525 ****************
;SAB82525 has a bug,to conquer it,the TSNX of Time_Slot Assignment Register
;Tranmit(TSAX) must be 1 less than the actual time slot,and,Clock Shift bit
;XCS2,XCS1,XCS0 should be initialized with 7.the same for receival
init_sab82525:
pshm SWWSR
stm #7f00h,SWWSR
Command_Execute:
stm #B_STAR,ar2
nop
nop
bit *ar2,15-2
nop
nop
;test STARb register bit2 CEC (Command Executing?)
bc Command_Execute,tc
stm #B_CCR1,ar2
nop
nop
st #35h,*ar2
; ST #0A5H,*AR2
;PU=0(standby), sc1 sc0=01(bus configuration,timemode1),clockmode5
nop
nop
stm #B_CCR2,ar2
nop
nop
st #38h,*ar2
; ST #08H,*AR2
;SOC1 SOC0=00,XCS0 RCS0=11,TIO=1,CIE=0,RIE=0,DIV=0
nop
nop
stm #B_TSAX,ar2
nop
nop
; st #07h,*ar2
ST #7CH,*AR2
nop
nop
;TSNX=B(20 or 21) , XCS2 XCS1=11 (XCS0=1) =>transmit clock shift is 7
stm #B_TSAR,ar2
; st #07h,*ar2
nop
nop
ST #7CH,*AR2
nop
nop
;TSNR=B(20 or 21) , RCS2 RCS1=11 (RCS0=1) =>shift 7
stm #B_XCCR,ar2
nop
nop
st #07h,*ar2
;Num of bits to be transmitted with a timeslot = 7+1= 8
nop
nop
stm #B_RCCR,ar2
nop
nop
st #07h,*ar2
;Num of bits to be received with a timeslot = 7+1= 8
nop
nop
stm #B_MASK,ar2
nop
nop
st #0ffH,*ar2 ;mask all a channel int.
nop
nop
stm #B_MASK,ar2
nop
nop
; st #0ffh,*ar2
st #038h,*ar2 ;enable RME,RPF,EXA,EXB
; ST #2FH,*AR2
nop
nop
stm #B_MODE,ar2 ;Transparent Mode 0, no address recognition , TMD=0 (external)
nop
nop
st #089h,*ar2 ;Loopback mode(internal)
; ST #0A8H,*AR2
; st #088h,*ar2
nop
nop
stm #B_RLCR,ar2
nop
nop
st #7fH,*ar2 ;receive length not check, 32*(1+1)=64 bytes
nop
nop
stm #B_XBCH,ar2
nop
nop
st #0,*ar2 ;DMA=0(Interrupt controlled transfer), CAS=0
nop
nop
stm #B_CMDR,ar2
nop
nop
st #041h,*ar2 ;RMC=1(Receive MSG Cmpt) , RHR=1(Rst HDLC rcver), XRES=1(Transmit Rst)
; ST #43H,*AR2
nop
nop
stm #B_CCR1,ar2
nop
nop
st #0b5h,*ar2 ;let PU=1 (Power up ---> active)
nop
nop
stm #B_STAR,ar2
nop
nop
hdlc_active_b
;******************************************
bit *ar2,15-2
bc hdlc_active_b,tc ; CEC =1?
;******************************************
nop
nop
popm SWWSR
ret
.end
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