saminit.c

S64和VS1003的MP3播放实现的源代码/

#ifdef AT91SAM7S32
#include "AT91SAM7S32.h"
#include "lib_AT91SAM7S32.h"
#endif

#ifdef AT91SAM7S64
#include "AT91SAM7S64.h"
#include "lib_AT91SAM7S64.h"
#endif

#include "SAMinit.h"

extern void SAM_AIC_IVR_Init(void);

void SAMInit(void)
{
#if SAM_REAMP > 0
    unsigned int *pARM_RESET_VECT = (unsigned int *)0; // 0 address
    unsigned int temp = 0;
#endif

    AT91PS_PMC   pPMC = AT91C_BASE_PMC;
    
    // reset all peripherals
    AT91C_BASE_RSTC->RSTC_RCR = (0xA5000000 | AT91C_RSTC_PERRST); 
    // wait reset command complete
    while(AT91C_BASE_RSTC->RSTC_RSR & AT91C_RSTC_SRCMP); 

    //* Set Flash Waite sate
	//  Single Cycle Access at Up to 30 MHz, or 40
	//  if MCK = 47923200 I have 50 Cycle for 1 usecond ( flied MC_FMR->FMCN
	AT91C_BASE_MC->MC_FMR = ((AT91C_MC_FMCN)&(48 <<16)) | AT91C_MC_FWS_0FWS ;

    //* Watchdog Disable
    AT91C_BASE_WDTC->WDTC_WDMR= AT91C_WDTC_WDDIS;

	//* Set MCK at 47 923 200
    // 1 Enabling the Main Oscillator:
        // SCK = 1/32768 = 30.51 uSecond
    	// Start up time = 8 * 6 / SCK = 56 * 30.51 = 1,46484375 ms
    pPMC->PMC_MOR = ( (AT91C_CKGR_OSCOUNT) & (0x06 <<8)) | AT91C_CKGR_MOSCEN ;
        // Wait the startup time
    while(!(pPMC->PMC_SR & AT91C_PMC_MOSCS));
	// 2 Checking the Main Oscillator Frequency (Optional)
	// 3 Setting PLL and divider:
		// - div by 5 Fin = 3,6864 =(18,432 / 5)
		// - Mul 25+1: Fout =	95,8464 =(3,6864 *26)
		// for 96 MHz the erroe is 0.16%
		// Field out NOT USED = 0
		// PLLCOUNT pll startup time estimate at : 0.844 ms
		// PLLCOUNT 28 = 0.000844 /(1/32768)
#if 1
    /* 18.432MHz XTAL */
    pPMC->PMC_PLLR = ((AT91C_CKGR_DIV & 0x05) |
                      (AT91C_CKGR_PLLCOUNT & (28<<8)) |
                      (AT91C_CKGR_MUL & (25<<16)));
#else
    /* 12MHz XTAL */
    pPMC->PMC_PLLR = ((AT91C_CKGR_DIV & 3) | (AT91C_CKGR_PLLCOUNT & (28<<8)) | (AT91C_CKGR_MUL & (24<<16)));
#endif
        // Wait the startup time
    while(!(pPMC->PMC_SR & AT91C_PMC_LOCK));
    while(!(pPMC->PMC_SR & AT91C_PMC_MCKRDY));
 	// 4. Selection of Master Clock and Processor Clock
 	// select the PLL clock divided by 2, 95.8464 / 2 = 47.9232MHz
 	pPMC->PMC_MCKR =  AT91C_PMC_PRES_CLK_2 ;
 	while(!(pPMC->PMC_SR & AT91C_PMC_MCKRDY));

 	pPMC->PMC_MCKR |= AT91C_PMC_CSS_PLL_CLK  ;
 	while(!(pPMC->PMC_SR & AT91C_PMC_MCKRDY));
 
    // 5. Interrupt system init
    SAM_AIC_IVR_Init();

	// 6. Test & ReMap
#if SAM_REAMP > 0
    temp = *pARM_RESET_VECT;
    *pARM_RESET_VECT = 0xA5A5A5A5;
    if (0xA5A5A5A5 == *pARM_RESET_VECT) 
    {
        // remap done
        *pARM_RESET_VECT = temp; // write back
    }
    else
    {
        AT91C_BASE_MC->MC_RCR = 1; // remap command
    }	  
#endif
}