sc-dsc.tan.qmsg

数字通信系统的设计及其性能和所传输的数字信号的统计特性有关。所谓 加扰技术

{  "Info" "ITDB_FULL_TCO_RESULT" "clk dscout dsc:inst2\|9 8.000 ns register " "Info: tco from clock clk to destination pin dscout through register dsc:inst2\|9 is 8.000 ns" { { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "clk source 3.000 ns + Longest register " "Info: + Longest clock path from clock clk to source register is 3.000 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(3.000 ns) 3.000 ns clk 1 CLK Pin_83 " "Info: 1: + IC(0.000 ns) + CELL(3.000 ns) = 3.000 ns; Loc. = Pin_83; CLK Node = 'clk'" {  } { { "E:\\3 实验 扰码与解扰（用Quartus II)\\SC\\db\\SC-DSC_cmp.qrpt" "" "" { Report "E:\\3 实验 扰码与解扰（用Quartus II)\\SC\\db\\SC-DSC_cmp.qrpt" Compiler "SC-DSC" "UNKNOWN" "V1" "E:\\3 实验 扰码与解扰（用Quartus II)\\SC\\db\\sc-dsc.quartus_db" { Floorplan "" "" "" { clk } "NODE_NAME" } } } { "E:\\3 实验 扰码与解扰（用Quartus II)\\SC\\SC-DSC.bdf" "" "" { Schematic "E:\\3 实验 扰码与解扰（用Quartus II)\\SC\\SC-DSC.bdf" { { { 208 -80 88 224 "clk" "" } } } } }  } 0} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.000 ns) 3.000 ns dsc:inst2\|9 2 REG LC51 " "Info: 2: + IC(0.000 ns) + CELL(0.000 ns) = 3.000 ns; Loc. = LC51; REG Node = 'dsc:inst2\|9'" {  } { { "E:\\3 实验 扰码与解扰（用Quartus II)\\SC\\db\\SC-DSC_cmp.qrpt" "" "" { Report "E:\\3 实验 扰码与解扰（用Quartus II)\\SC\\db\\SC-DSC_cmp.qrpt" Compiler "SC-DSC" "UNKNOWN" "V1" "E:\\3 实验 扰码与解扰（用Quartus II)\\SC\\db\\sc-dsc.quartus_db" { Floorplan "" "" "0.000 ns" { clk dsc:inst2|9 } "NODE_NAME" } } } { "E:\\3 实验 扰码与解扰（用Quartus II)\\SC\\dsc.bdf" "" "" { Schematic "E:\\3 实验 扰码与解扰（用Quartus II)\\SC\\dsc.bdf" { { { 168 488 552 248 "9" "" } } } } }  } 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "3.000 ns " "Info: Total cell delay = 3.000 ns" {  } {  } 0}  } { { "E:\\3 实验 扰码与解扰（用Quartus II)\\SC\\db\\SC-DSC_cmp.qrpt" "" "" { Report "E:\\3 实验 扰码与解扰（用Quartus II)\\SC\\db\\SC-DSC_cmp.qrpt" Compiler "SC-DSC" "UNKNOWN" "V1" "E:\\3 实验 扰码与解扰（用Quartus II)\\SC\\db\\sc-dsc.quartus_db" { Floorplan "" "" "3.000 ns" { clk clk~out dsc:inst2|9 } "NODE_NAME" } } }  } 0} { "Info" "ITDB_FULL_TCO_DELAY" "1.000 ns + " "Info: + Micro clock to output delay of source is 1.000 ns" {  } { { "E:\\3 实验 扰码与解扰（用Quartus II)\\SC\\dsc.bdf" "" "" { Schematic "E:\\3 实验 扰码与解扰（用Quartus II)\\SC\\dsc.bdf" { { { 168 488 552 248 "9" "" } } } } }  } 0} { "Info" "ITDB_FULL_DATA_PATH_RESULT" "4.000 ns + Longest register pin " "Info: + Longest register to pin delay is 4.000 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.000 ns) 0.000 ns dsc:inst2\|9 1 REG LC51 " "Info: 1: + IC(0.000 ns) + CELL(0.000 ns) = 0.000 ns; Loc. = LC51; REG Node = 'dsc:inst2\|9'" {  } { { "E:\\3 实验 扰码与解扰（用Quartus II)\\SC\\db\\SC-DSC_cmp.qrpt" "" "" { Report "E:\\3 实验 扰码与解扰（用Quartus II)\\SC\\db\\SC-DSC_cmp.qrpt" Compiler "SC-DSC" "UNKNOWN" "V1" "E:\\3 实验 扰码与解扰（用Quartus II)\\SC\\db\\sc-dsc.quartus_db" { Floorplan "" "" "" { dsc:inst2|9 } "NODE_NAME" } } } { "E:\\3 实验 扰码与解扰（用Quartus II)\\SC\\dsc.bdf" "" "" { Schematic "E:\\3 实验 扰码与解扰（用Quartus II)\\SC\\dsc.bdf" { { { 168 488 552 248 "9" "" } } } } }  } 0} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(4.000 ns) 4.000 ns dscout 2 PIN Pin_40 " "Info: 2: + IC(0.000 ns) + CELL(4.000 ns) = 4.000 ns; Loc. = Pin_40; PIN Node = 'dscout'" {  } { { "E:\\3 实验 扰码与解扰（用Quartus II)\\SC\\db\\SC-DSC_cmp.qrpt" "" "" { Report "E:\\3 实验 扰码与解扰（用Quartus II)\\SC\\db\\SC-DSC_cmp.qrpt" Compiler "SC-DSC" "UNKNOWN" "V1" "E:\\3 实验 扰码与解扰（用Quartus II)\\SC\\db\\sc-dsc.quartus_db" { Floorplan "" "" "4.000 ns" { dsc:inst2|9 dscout } "NODE_NAME" } } } { "E:\\3 实验 扰码与解扰（用Quartus II)\\SC\\SC-DSC.bdf" "" "" { Schematic "E:\\3 实验 扰码与解扰（用Quartus II)\\SC\\SC-DSC.bdf" { { { 208 600 776 224 "dscout" "" } } } } }  } 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "4.000 ns " "Info: Total cell delay = 4.000 ns" {  } {  } 0}  } { { "E:\\3 实验 扰码与解扰（用Quartus II)\\SC\\db\\SC-DSC_cmp.qrpt" "" "" { Report "E:\\3 实验 扰码与解扰（用Quartus II)\\SC\\db\\SC-DSC_cmp.qrpt" Compiler "SC-DSC" "UNKNOWN" "V1" "E:\\3 实验 扰码与解扰（用Quartus II)\\SC\\db\\sc-dsc.quartus_db" { Floorplan "" "" "4.000 ns" { dsc:inst2|9 dscout } "NODE_NAME" } } }  } 0}  } { { "E:\\3 实验 扰码与解扰（用Quartus II)\\SC\\db\\SC-DSC_cmp.qrpt" "" "" { Report "E:\\3 实验 扰码与解扰（用Quartus II)\\SC\\db\\SC-DSC_cmp.qrpt" Compiler "SC-DSC" "UNKNOWN" "V1" "E:\\3 实验 扰码与解扰（用Quartus II)\\SC\\db\\sc-dsc.quartus_db" { Floorplan "" "" "3.000 ns" { clk clk~out dsc:inst2|9 } "NODE_NAME" } } } { "E:\\3 实验 扰码与解扰（用Quartus II)\\SC\\db\\SC-DSC_cmp.qrpt" "" "" { Report "E:\\3 实验 扰码与解扰（用Quartus II)\\SC\\db\\SC-DSC_cmp.qrpt" Compiler "SC-DSC" "UNKNOWN" "V1" "E:\\3 实验 扰码与解扰（用Quartus II)\\SC\\db\\sc-dsc.quartus_db" { Floorplan "" "" "4.000 ns" { dsc:inst2|9 dscout } "NODE_NAME" } } }  } 0 }
{  "Info" "ITDB_FULL_MIN_TCO_RESULT" "clk nrz nrz:inst\|5 8.000 ns register " "Info: Minimum tco from clock clk to destination pin nrz through register nrz:inst\|5 is 8.000 ns" { { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "clk source 3.000 ns + Shortest register " "Info: + Shortest clock path from clock clk to source register is 3.000 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(3.000 ns) 3.000 ns clk 1 CLK Pin_83 " "Info: 1: + IC(0.000 ns) + CELL(3.000 ns) = 3.000 ns; Loc. = Pin_83; CLK Node = 'clk'" {  } { { "E:\\3 实验 扰码与解扰（用Quartus II)\\SC\\db\\SC-DSC_cmp.qrpt" "" "" { Report "E:\\3 实验 扰码与解扰（用Quartus II)\\SC\\db\\SC-DSC_cmp.qrpt" Compiler "SC-DSC" "UNKNOWN" "V1" "E:\\3 实验 扰码与解扰（用Quartus II)\\SC\\db\\sc-dsc.quartus_db" { Floorplan "" "" "" { clk } "NODE_NAME" } } } { "E:\\3 实验 扰码与解扰（用Quartus II)\\SC\\SC-DSC.bdf" "" "" { Schematic "E:\\3 实验 扰码与解扰（用Quartus II)\\SC\\SC-DSC.bdf" { { { 208 -80 88 224 "clk" "" } } } } }  } 0} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.000 ns) 3.000 ns nrz:inst\|5 2 REG LC56 " "Info: 2: + IC(0.000 ns) + CELL(0.000 ns) = 3.000 ns; Loc. = LC56; REG Node = 'nrz:inst\|5'" {  } { { "E:\\3 实验 扰码与解扰（用Quartus II)\\SC\\db\\SC-DSC_cmp.qrpt" "" "" { Report "E:\\3 实验 扰码与解扰（用Quartus II)\\SC\\db\\SC-DSC_cmp.qrpt" Compiler "SC-DSC" "UNKNOWN" "V1" "E:\\3 实验 扰码与解扰（用Quartus II)\\SC\\db\\sc-dsc.quartus_db" { Floorplan "" "" "0.000 ns" { clk nrz:inst|5 } "NODE_NAME" } } } { "E:\\3 实验 扰码与解扰（用Quartus II)\\SC\\nrz.bdf" "" "" { Schematic "E:\\3 实验 扰码与解扰（用Quartus II)\\SC\\nrz.bdf" { { { 104 608 672 184 "5" "" } } } } }  } 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "3.000 ns " "Info: Total cell delay = 3.000 ns" {  } {  } 0}  } { { "E:\\3 实验 扰码与解扰（用Quartus II)\\SC\\db\\SC-DSC_cmp.qrpt" "" "" { Report "E:\\3 实验 扰码与解扰（用Quartus II)\\SC\\db\\SC-DSC_cmp.qrpt" Compiler "SC-DSC" "UNKNOWN" "V1" "E:\\3 实验 扰码与解扰（用Quartus II)\\SC\\db\\sc-dsc.quartus_db" { Floorplan "" "" "3.000 ns" { clk clk~out nrz:inst|5 } "NODE_NAME" } } }  } 0} { "Info" "ITDB_FULL_TCO_DELAY" "1.000 ns + " "Info: + Micro clock to output delay of source is 1.000 ns" {  } { { "E:\\3 实验 扰码与解扰（用Quartus II)\\SC\\nrz.bdf" "" "" { Schematic "E:\\3 实验 扰码与解扰（用Quartus II)\\SC\\nrz.bdf" { { { 104 608 672 184 "5" "" } } } } }  } 0} { "Info" "ITDB_FULL_DATA_PATH_RESULT" "4.000 ns + Shortest register pin " "Info: + Shortest register to pin delay is 4.000 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.000 ns) 0.000 ns nrz:inst\|5 1 REG LC56 " "Info: 1: + IC(0.000 ns) + CELL(0.000 ns) = 0.000 ns; Loc. = LC56; REG Node = 'nrz:inst\|5'" {  } { { "E:\\3 实验 扰码与解扰（用Quartus II)\\SC\\db\\SC-DSC_cmp.qrpt" "" "" { Report "E:\\3 实验 扰码与解扰（用Quartus II)\\SC\\db\\SC-DSC_cmp.qrpt" Compiler "SC-DSC" "UNKNOWN" "V1" "E:\\3 实验 扰码与解扰（用Quartus II)\\SC\\db\\sc-dsc.quartus_db" { Floorplan "" "" "" { nrz:inst|5 } "NODE_NAME" } } } { "E:\\3 实验 扰码与解扰（用Quartus II)\\SC\\nrz.bdf" "" "" { Schematic "E:\\3 实验 扰码与解扰（用Quartus II)\\SC\\nrz.bdf" { { { 104 608 672 184 "5" "" } } } } }  } 0} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(4.000 ns) 4.000 ns nrz 2 PIN Pin_37 " "Info: 2: + IC(0.000 ns) + CELL(4.000 ns) = 4.000 ns; Loc. = Pin_37; PIN Node = 'nrz'" {  } { { "E:\\3 实验 扰码与解扰（用Quartus II)\\SC\\db\\SC-DSC_cmp.qrpt" "" "" { Report "E:\\3 实验 扰码与解扰（用Quartus II)\\SC\\db\\SC-DSC_cmp.qrpt" Compiler "SC-DSC" "UNKNOWN" "V1" "E:\\3 实验 扰码与解扰（用Quartus II)\\SC\\db\\sc-dsc.quartus_db" { Floorplan "" "" "4.000 ns" { nrz:inst|5 nrz } "NODE_NAME" } } } { "E:\\3 实验 扰码与解扰（用Quartus II)\\SC\\SC-DSC.bdf" "" "" { Schematic "E:\\3 实验 扰码与解扰（用Quartus II)\\SC\\SC-DSC.bdf" { { { 56 264 440 72 "nrz" "" } } } } }  } 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "4.000 ns " "Info: Total cell delay = 4.000 ns" {  } {  } 0}  } { { "E:\\3 实验 扰码与解扰（用Quartus II)\\SC\\db\\SC-DSC_cmp.qrpt" "" "" { Report "E:\\3 实验 扰码与解扰（用Quartus II)\\SC\\db\\SC-DSC_cmp.qrpt" Compiler "SC-DSC" "UNKNOWN" "V1" "E:\\3 实验 扰码与解扰（用Quartus II)\\SC\\db\\sc-dsc.quartus_db" { Floorplan "" "" "4.000 ns" { nrz:inst|5 nrz } "NODE_NAME" } } }  } 0}  } { { "E:\\3 实验 扰码与解扰（用Quartus II)\\SC\\db\\SC-DSC_cmp.qrpt" "" "" { Report "E:\\3 实验 扰码与解扰（用Quartus II)\\SC\\db\\SC-DSC_cmp.qrpt" Compiler "SC-DSC" "UNKNOWN" "V1" "E:\\3 实验 扰码与解扰（用Quartus II)\\SC\\db\\sc-dsc.quartus_db" { Floorplan "" "" "3.000 ns" { clk clk~out nrz:inst|5 } "NODE_NAME" } } } { "E:\\3 实验 扰码与解扰（用Quartus II)\\SC\\db\\SC-DSC_cmp.qrpt" "" "" { Report "E:\\3 实验 扰码与解扰（用Quartus II)\\SC\\db\\SC-DSC_cmp.qrpt" Compiler "SC-DSC" "UNKNOWN" "V1" "E:\\3 实验 扰码与解扰（用Quartus II)\\SC\\db\\sc-dsc.quartus_db" { Floorplan "" "" "4.000 ns" { nrz:inst|5 nrz } "NODE_NAME" } } }  } 0 }
{  "Info" "IQEXE_ERROR_COUNT" "Timing Analyzer 0 s 1  " "Info: Quartus II Timing Analyzer was successful. 0 errors, 1 warning" { { "Info" "IQEXE_END_BANNER_TIME" "Fri Jun 01 14:01:37 2007 " "Info: Processing ended: Fri Jun 01 14:01:37 2007" {  } {  } 0} { "Info" "IQEXE_ELAPSED_TIME" "00:00:01 " "Info: Elapsed time: 00:00:01" {  } {  } 0}  } {  } 0 }
{  "Info" "IQCU_REPORT_WRITTEN_TO" "SC-DSC.tan.rpt " "Info: Writing report file SC-DSC.tan.rpt" {  } {  } 0 }