sc-dsc.tan.qmsg

数字通信系统的设计及其性能和所传输的数字信号的统计特性有关。所谓 加扰技术

{  "Info" "IQEXE_SEPARATOR" "" "Info: *******************************************************************" {  } {  } 0 }
{  "Info" "IQEXE_START_BANNER_PRODUCT" "Timing Analyzer " "Info: Running Quartus II Timing Analyzer" { { "Info" "IQEXE_START_BANNER_VERSION" "Version 3.0 Build 199 06/26/2003 SJ Full Version " "Info: Version 3.0 Build 199 06/26/2003 SJ Full Version" {  } {  } 0} { "Info" "IQEXE_START_BANNER_TIME" "Fri Jun 01 14:01:36 2007 " "Info: Processing started: Fri Jun 01 14:01:36 2007" {  } {  } 0}  } {  } 0 }
{  "Info" "IQEXE_START_BANNER_COMMANDLINE" "quartus_tan --import_settings_files=off --export_settings_files=off sc-dsc -c SC-DSC " "Info: Command: quartus_tan --import_settings_files=off --export_settings_files=off sc-dsc -c SC-DSC" {  } {  } 0 }
{  "Warning" "WTDB_NO_CLOCKS" "" "Warning: Found pins functioning as undefined clocks and/or memory enables" { { "Info" "ITDB_NODE_MAP_TO_CLK" "clk " "Info: Assuming node clk is an undefined clock" {  } { { "E:\\3 实验 扰码与解扰（用Quartus II)\\SC\\SC-DSC.bdf" "" "" { Schematic "E:\\3 实验 扰码与解扰（用Quartus II)\\SC\\SC-DSC.bdf" { { { 208 -80 88 224 "clk" "" } } } } } { "c:\\quartus\\bin\\Assignment Editor.qase" "" "" { Assignment "c:\\quartus\\bin\\Assignment Editor.qase" 1 { { { 0 "clk" } } } } }  } 0}  } {  } 0 }
{  "Info" "ITDB_FULL_CLOCK_REG_RESULT" "clk register dsc:inst2\|1 register dsc:inst2\|9 76.92 MHz 13.0 ns Internal " "Info: Clock clk has Internal fmax of 76.92 MHz between source register dsc:inst2\|1 and destination register dsc:inst2\|9 (period= 13.0 ns)" { { "Info" "ITDB_FULL_DATA_PATH_RESULT" "8.000 ns + Longest register register " "Info: + Longest register to register delay is 8.000 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.000 ns) 0.000 ns dsc:inst2\|1 1 REG LC55 " "Info: 1: + IC(0.000 ns) + CELL(0.000 ns) = 0.000 ns; Loc. = LC55; REG Node = 'dsc:inst2\|1'" {  } { { "E:\\3 实验 扰码与解扰（用Quartus II)\\SC\\db\\SC-DSC_cmp.qrpt" "" "" { Report "E:\\3 实验 扰码与解扰（用Quartus II)\\SC\\db\\SC-DSC_cmp.qrpt" Compiler "SC-DSC" "UNKNOWN" "V1" "E:\\3 实验 扰码与解扰（用Quartus II)\\SC\\db\\sc-dsc.quartus_db" { Floorplan "" "" "" { dsc:inst2|1 } "NODE_NAME" } } } { "E:\\3 实验 扰码与解扰（用Quartus II)\\SC\\dsc.bdf" "" "" { Schematic "E:\\3 实验 扰码与解扰（用Quartus II)\\SC\\dsc.bdf" { { { 32 336 400 112 "1" "" } } } } }  } 0} { "Info" "ITDB_NODE_DELAY" "IC(2.000 ns) + CELL(6.000 ns) 8.000 ns dsc:inst2\|9 2 REG LC51 " "Info: 2: + IC(2.000 ns) + CELL(6.000 ns) = 8.000 ns; Loc. = LC51; REG Node = 'dsc:inst2\|9'" {  } { { "E:\\3 实验 扰码与解扰（用Quartus II)\\SC\\db\\SC-DSC_cmp.qrpt" "" "" { Report "E:\\3 实验 扰码与解扰（用Quartus II)\\SC\\db\\SC-DSC_cmp.qrpt" Compiler "SC-DSC" "UNKNOWN" "V1" "E:\\3 实验 扰码与解扰（用Quartus II)\\SC\\db\\sc-dsc.quartus_db" { Floorplan "" "" "8.000 ns" { dsc:inst2|1 dsc:inst2|9 } "NODE_NAME" } } } { "E:\\3 实验 扰码与解扰（用Quartus II)\\SC\\dsc.bdf" "" "" { Schematic "E:\\3 实验 扰码与解扰（用Quartus II)\\SC\\dsc.bdf" { { { 168 488 552 248 "9" "" } } } } }  } 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "6.000 ns " "Info: Total cell delay = 6.000 ns" {  } {  } 0} { "Info" "ITDB_TOTAL_IC_DELAY" "2.000 ns " "Info: Total interconnect delay = 2.000 ns" {  } {  } 0}  } { { "E:\\3 实验 扰码与解扰（用Quartus II)\\SC\\db\\SC-DSC_cmp.qrpt" "" "" { Report "E:\\3 实验 扰码与解扰（用Quartus II)\\SC\\db\\SC-DSC_cmp.qrpt" Compiler "SC-DSC" "UNKNOWN" "V1" "E:\\3 实验 扰码与解扰（用Quartus II)\\SC\\db\\sc-dsc.quartus_db" { Floorplan "" "" "8.000 ns" { dsc:inst2|1 dsc:inst2|9 } "NODE_NAME" } } }  } 0} { "Info" "ITDB_FULL_CLOCK_SKEW_RESULT" "0.000 ns - Smallest " "Info: - Smallest clock skew is 0.000 ns" { { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "clk destination 3.000 ns + Shortest register " "Info: + Shortest clock path from clock clk to destination register is 3.000 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(3.000 ns) 3.000 ns clk 1 CLK Pin_83 " "Info: 1: + IC(0.000 ns) + CELL(3.000 ns) = 3.000 ns; Loc. = Pin_83; CLK Node = 'clk'" {  } { { "E:\\3 实验 扰码与解扰（用Quartus II)\\SC\\db\\SC-DSC_cmp.qrpt" "" "" { Report "E:\\3 实验 扰码与解扰（用Quartus II)\\SC\\db\\SC-DSC_cmp.qrpt" Compiler "SC-DSC" "UNKNOWN" "V1" "E:\\3 实验 扰码与解扰（用Quartus II)\\SC\\db\\sc-dsc.quartus_db" { Floorplan "" "" "" { clk } "NODE_NAME" } } } { "E:\\3 实验 扰码与解扰（用Quartus II)\\SC\\SC-DSC.bdf" "" "" { Schematic "E:\\3 实验 扰码与解扰（用Quartus II)\\SC\\SC-DSC.bdf" { { { 208 -80 88 224 "clk" "" } } } } }  } 0} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.000 ns) 3.000 ns dsc:inst2\|9 2 REG LC51 " "Info: 2: + IC(0.000 ns) + CELL(0.000 ns) = 3.000 ns; Loc. = LC51; REG Node = 'dsc:inst2\|9'" {  } { { "E:\\3 实验 扰码与解扰（用Quartus II)\\SC\\db\\SC-DSC_cmp.qrpt" "" "" { Report "E:\\3 实验 扰码与解扰（用Quartus II)\\SC\\db\\SC-DSC_cmp.qrpt" Compiler "SC-DSC" "UNKNOWN" "V1" "E:\\3 实验 扰码与解扰（用Quartus II)\\SC\\db\\sc-dsc.quartus_db" { Floorplan "" "" "0.000 ns" { clk dsc:inst2|9 } "NODE_NAME" } } } { "E:\\3 实验 扰码与解扰（用Quartus II)\\SC\\dsc.bdf" "" "" { Schematic "E:\\3 实验 扰码与解扰（用Quartus II)\\SC\\dsc.bdf" { { { 168 488 552 248 "9" "" } } } } }  } 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "3.000 ns " "Info: Total cell delay = 3.000 ns" {  } {  } 0}  } { { "E:\\3 实验 扰码与解扰（用Quartus II)\\SC\\db\\SC-DSC_cmp.qrpt" "" "" { Report "E:\\3 实验 扰码与解扰（用Quartus II)\\SC\\db\\SC-DSC_cmp.qrpt" Compiler "SC-DSC" "UNKNOWN" "V1" "E:\\3 实验 扰码与解扰（用Quartus II)\\SC\\db\\sc-dsc.quartus_db" { Floorplan "" "" "3.000 ns" { clk clk~out dsc:inst2|9 } "NODE_NAME" } } }  } 0} { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "clk source 3.000 ns - Longest register " "Info: - Longest clock path from clock clk to source register is 3.000 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(3.000 ns) 3.000 ns clk 1 CLK Pin_83 " "Info: 1: + IC(0.000 ns) + CELL(3.000 ns) = 3.000 ns; Loc. = Pin_83; CLK Node = 'clk'" {  } { { "E:\\3 实验 扰码与解扰（用Quartus II)\\SC\\db\\SC-DSC_cmp.qrpt" "" "" { Report "E:\\3 实验 扰码与解扰（用Quartus II)\\SC\\db\\SC-DSC_cmp.qrpt" Compiler "SC-DSC" "UNKNOWN" "V1" "E:\\3 实验 扰码与解扰（用Quartus II)\\SC\\db\\sc-dsc.quartus_db" { Floorplan "" "" "" { clk } "NODE_NAME" } } } { "E:\\3 实验 扰码与解扰（用Quartus II)\\SC\\SC-DSC.bdf" "" "" { Schematic "E:\\3 实验 扰码与解扰（用Quartus II)\\SC\\SC-DSC.bdf" { { { 208 -80 88 224 "clk" "" } } } } }  } 0} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.000 ns) 3.000 ns dsc:inst2\|1 2 REG LC55 " "Info: 2: + IC(0.000 ns) + CELL(0.000 ns) = 3.000 ns; Loc. = LC55; REG Node = 'dsc:inst2\|1'" {  } { { "E:\\3 实验 扰码与解扰（用Quartus II)\\SC\\db\\SC-DSC_cmp.qrpt" "" "" { Report "E:\\3 实验 扰码与解扰（用Quartus II)\\SC\\db\\SC-DSC_cmp.qrpt" Compiler "SC-DSC" "UNKNOWN" "V1" "E:\\3 实验 扰码与解扰（用Quartus II)\\SC\\db\\sc-dsc.quartus_db" { Floorplan "" "" "0.000 ns" { clk dsc:inst2|1 } "NODE_NAME" } } } { "E:\\3 实验 扰码与解扰（用Quartus II)\\SC\\dsc.bdf" "" "" { Schematic "E:\\3 实验 扰码与解扰（用Quartus II)\\SC\\dsc.bdf" { { { 32 336 400 112 "1" "" } } } } }  } 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "3.000 ns " "Info: Total cell delay = 3.000 ns" {  } {  } 0}  } { { "E:\\3 实验 扰码与解扰（用Quartus II)\\SC\\db\\SC-DSC_cmp.qrpt" "" "" { Report "E:\\3 实验 扰码与解扰（用Quartus II)\\SC\\db\\SC-DSC_cmp.qrpt" Compiler "SC-DSC" "UNKNOWN" "V1" "E:\\3 实验 扰码与解扰（用Quartus II)\\SC\\db\\sc-dsc.quartus_db" { Floorplan "" "" "3.000 ns" { clk clk~out dsc:inst2|1 } "NODE_NAME" } } }  } 0}  } { { "E:\\3 实验 扰码与解扰（用Quartus II)\\SC\\db\\SC-DSC_cmp.qrpt" "" "" { Report "E:\\3 实验 扰码与解扰（用Quartus II)\\SC\\db\\SC-DSC_cmp.qrpt" Compiler "SC-DSC" "UNKNOWN" "V1" "E:\\3 实验 扰码与解扰（用Quartus II)\\SC\\db\\sc-dsc.quartus_db" { Floorplan "" "" "3.000 ns" { clk clk~out dsc:inst2|9 } "NODE_NAME" } } } { "E:\\3 实验 扰码与解扰（用Quartus II)\\SC\\db\\SC-DSC_cmp.qrpt" "" "" { Report "E:\\3 实验 扰码与解扰（用Quartus II)\\SC\\db\\SC-DSC_cmp.qrpt" Compiler "SC-DSC" "UNKNOWN" "V1" "E:\\3 实验 扰码与解扰（用Quartus II)\\SC\\db\\sc-dsc.quartus_db" { Floorplan "" "" "3.000 ns" { clk clk~out dsc:inst2|1 } "NODE_NAME" } } }  } 0} { "Info" "ITDB_FULL_TCO_DELAY" "1.000 ns + " "Info: + Micro clock to output delay of source is 1.000 ns" {  } { { "E:\\3 实验 扰码与解扰（用Quartus II)\\SC\\dsc.bdf" "" "" { Schematic "E:\\3 实验 扰码与解扰（用Quartus II)\\SC\\dsc.bdf" { { { 32 336 400 112 "1" "" } } } } }  } 0} { "Info" "ITDB_FULL_TSU_DELAY" "4.000 ns + " "Info: + Micro setup delay of destination is 4.000 ns" {  } { { "E:\\3 实验 扰码与解扰（用Quartus II)\\SC\\dsc.bdf" "" "" { Schematic "E:\\3 实验 扰码与解扰（用Quartus II)\\SC\\dsc.bdf" { { { 168 488 552 248 "9" "" } } } } }  } 0}  } { { "E:\\3 实验 扰码与解扰（用Quartus II)\\SC\\db\\SC-DSC_cmp.qrpt" "" "" { Report "E:\\3 实验 扰码与解扰（用Quartus II)\\SC\\db\\SC-DSC_cmp.qrpt" Compiler "SC-DSC" "UNKNOWN" "V1" "E:\\3 实验 扰码与解扰（用Quartus II)\\SC\\db\\sc-dsc.quartus_db" { Floorplan "" "" "8.000 ns" { dsc:inst2|1 dsc:inst2|9 } "NODE_NAME" } } } { "E:\\3 实验 扰码与解扰（用Quartus II)\\SC\\db\\SC-DSC_cmp.qrpt" "" "" { Report "E:\\3 实验 扰码与解扰（用Quartus II)\\SC\\db\\SC-DSC_cmp.qrpt" Compiler "SC-DSC" "UNKNOWN" "V1" "E:\\3 实验 扰码与解扰（用Quartus II)\\SC\\db\\sc-dsc.quartus_db" { Floorplan "" "" "3.000 ns" { clk clk~out dsc:inst2|9 } "NODE_NAME" } } } { "E:\\3 实验 扰码与解扰（用Quartus II)\\SC\\db\\SC-DSC_cmp.qrpt" "" "" { Report "E:\\3 实验 扰码与解扰（用Quartus II)\\SC\\db\\SC-DSC_cmp.qrpt" Compiler "SC-DSC" "UNKNOWN" "V1" "E:\\3 实验 扰码与解扰（用Quartus II)\\SC\\db\\sc-dsc.quartus_db" { Floorplan "" "" "3.000 ns" { clk clk~out dsc:inst2|1 } "NODE_NAME" } } }  } 0 }