sc-dsc.map.qmsg

数字通信系统的设计及其性能和所传输的数字信号的统计特性有关。所谓 加扰技术

{  "Info" "IQEXE_SEPARATOR" "" "Info: *******************************************************************" {  } {  } 0 }
{  "Info" "IQEXE_START_BANNER_PRODUCT" "Analysis & Synthesis " "Info: Running Quartus II Analysis & Synthesis" { { "Info" "IQEXE_START_BANNER_VERSION" "Version 3.0 Build 199 06/26/2003 SJ Full Version " "Info: Version 3.0 Build 199 06/26/2003 SJ Full Version" {  } {  } 0} { "Info" "IQEXE_START_BANNER_TIME" "Fri Jun 01 14:01:28 2007 " "Info: Processing started: Fri Jun 01 14:01:28 2007" {  } {  } 0}  } {  } 0 }
{  "Info" "IQEXE_START_BANNER_COMMANDLINE" "quartus_map --import_settings_files=on --export_settings_files=off sc-dsc -c SC-DSC " "Info: Command: quartus_map --import_settings_files=on --export_settings_files=off sc-dsc -c SC-DSC" {  } {  } 0 }
{  "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "E:\\3 实验 扰码与解扰（用Quartus II)\\SC\\SC-DSC.bdf 1 1 " "Info: Found 1 design units and 1 entities in source file E:\\3 实验 扰码与解扰（用Quartus II)\\SC\\SC-DSC.bdf" { { "Info" "ISGN_ENTITY_NAME" "1 SC-DSC " "Info: Found entity 1: SC-DSC" {  } { { "E:\\3 实验 扰码与解扰（用Quartus II)\\SC\\SC-DSC.bdf" "SC-DSC" "" { Schematic "E:\\3 实验 扰码与解扰（用Quartus II)\\SC\\SC-DSC.bdf" { { } } } }  } 0}  } {  } 0 }
{  "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "E:\\3 实验 扰码与解扰（用Quartus II)\\SC\\nrz.bdf 1 1 " "Info: Found 1 design units and 1 entities in source file E:\\3 实验 扰码与解扰（用Quartus II)\\SC\\nrz.bdf" { { "Info" "ISGN_ENTITY_NAME" "1 nrz " "Info: Found entity 1: nrz" {  } { { "E:\\3 实验 扰码与解扰（用Quartus II)\\SC\\nrz.bdf" "nrz" "" { Schematic "E:\\3 实验 扰码与解扰（用Quartus II)\\SC\\nrz.bdf" { { } } } }  } 0}  } {  } 0 }
{  "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "E:\\3 实验 扰码与解扰（用Quartus II)\\SC\\SC.gdf 1 1 " "Info: Found 1 design units and 1 entities in source file E:\\3 实验 扰码与解扰（用Quartus II)\\SC\\SC.gdf" { { "Info" "ISGN_ENTITY_NAME" "1 SC " "Info: Found entity 1: SC" {  } { { "E:\\3 实验 扰码与解扰（用Quartus II)\\SC\\SC.gdf" "SC" "" { Schematic "E:\\3 实验 扰码与解扰（用Quartus II)\\SC\\SC.gdf" { { } } } }  } 0}  } {  } 0 }
{  "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "E:\\3 实验 扰码与解扰（用Quartus II)\\SC\\dsc.bdf 1 1 " "Info: Found 1 design units and 1 entities in source file E:\\3 实验 扰码与解扰（用Quartus II)\\SC\\dsc.bdf" { { "Info" "ISGN_ENTITY_NAME" "1 dsc " "Info: Found entity 1: dsc" {  } { { "E:\\3 实验 扰码与解扰（用Quartus II)\\SC\\dsc.bdf" "dsc" "" { Schematic "E:\\3 实验 扰码与解扰（用Quartus II)\\SC\\dsc.bdf" { { } } } }  } 0}  } {  } 0 }
{  "Info" "IRTL_INFERENCING_SUMMARY" "0 " "Info: Inferred 0 megafunctions from design logic" {  } {  } 0 }
{  "Info" "ISCL_SCL_TM_SUMMARY" "21 " "Info: Implemented 21 device resources after synthesis - the final resource count might be different" { { "Info" "ISCL_SCL_TM_IPINS" "1 " "Info: Implemented 1 input pins" {  } {  } 0} { "Info" "ISCL_SCL_TM_OPINS" "3 " "Info: Implemented 3 output pins" {  } {  } 0} { "Info" "ISCL_SCL_TM_MCELLS" "17 " "Info: Implemented 17 macrocells" {  } {  } 0}  } {  } 0 }
{  "Info" "IQEXE_ERROR_COUNT" "Analysis & Synthesis 0 s 0 s " "Info: Quartus II Analysis & Synthesis was successful. 0 errors, 0 warnings" { { "Info" "IQEXE_END_BANNER_TIME" "Fri Jun 01 14:01:29 2007 " "Info: Processing ended: Fri Jun 01 14:01:29 2007" {  } {  } 0} { "Info" "IQEXE_ELAPSED_TIME" "00:00:01 " "Info: Elapsed time: 00:00:01" {  } {  } 0}  } {  } 0 }
{  "Info" "IQCU_REPORT_WRITTEN_TO" "SC-DSC.map.rpt " "Info: Writing report file SC-DSC.map.rpt" {  } {  } 0 }