sc-dsc.fit.eqn

数字通信系统的设计及其性能和所传输的数字信号的统计特性有关。所谓 加扰技术

--B1_14 is nrz:inst|14 at LC64
B1_14_p2_out = !B1_4 & B1_5;
B1_14_p3_out = !B1_4 & B1_3;
B1_14_p4_out = !B1_4 & B1_14;
B1_14_or_out = B1_14_p2_out # B1_14_p3_out # B1_14_p4_out;
B1_14_reg_input = !B1_5 $ B1_14_or_out;
B1_14 = DFFE(B1_14_reg_input, GLOBAL(clk), , , );


--B1_3 is nrz:inst|3 at LC63
B1_3_or_out = B1_14;
B1_3_reg_input = B1_3_or_out;
B1_3 = DFFE(B1_3_reg_input, GLOBAL(clk), , , );


--B1_4 is nrz:inst|4 at LC62
B1_4_or_out = B1_3;
B1_4_reg_input = B1_4_or_out;
B1_4 = DFFE(B1_4_reg_input, GLOBAL(clk), , , );


--B1_5 is nrz:inst|5 at LC56
B1_5_or_out = B1_4;
B1_5_reg_input = B1_5_or_out;
B1_5 = DFFE(B1_5_reg_input, GLOBAL(clk), , , );


--C1_17 is SC:inst1|17 at LC61
C1_17_or_out = B1_5;
C1_17_reg_input = C1_17_or_out;
C1_17 = DFFE(C1_17_reg_input, GLOBAL(clk), , , );


--C1_8 is SC:inst1|8 at LC60
C1_8_p2_out = C1_10 & !C1_17;
C1_8_p3_out = !C1_10 & C1_17;
C1_8_or_out = C1_8_p2_out # C1_8_p3_out;
C1_8_reg_input = C1_12 $ C1_8_or_out;
C1_8 = DFFE(C1_8_reg_input, GLOBAL(clk), , , );


--C1_9 is SC:inst1|9 at LC59
C1_9_or_out = C1_8;
C1_9_reg_input = C1_9_or_out;
C1_9 = DFFE(C1_9_reg_input, GLOBAL(clk), , , );


--C1_10 is SC:inst1|10 at LC58
C1_10_or_out = C1_9;
C1_10_reg_input = C1_10_or_out;
C1_10 = DFFE(C1_10_reg_input, GLOBAL(clk), , , );


--C1_11 is SC:inst1|11 at LC57
C1_11_or_out = C1_10;
C1_11_reg_input = C1_11_or_out;
C1_11 = DFFE(C1_11_reg_input, GLOBAL(clk), , , );


--C1_12 is SC:inst1|12 at LC53
C1_12_or_out = C1_11;
C1_12_reg_input = C1_12_or_out;
C1_12 = DFFE(C1_12_reg_input, GLOBAL(clk), , , );


--D1_1 is dsc:inst2|1 at LC55
D1_1_or_out = C1_12;
D1_1_reg_input = D1_1_or_out;
D1_1 = DFFE(D1_1_reg_input, GLOBAL(clk), , , );


--D1_3 is dsc:inst2|3 at LC54
D1_3_or_out = D1_1;
D1_3_reg_input = D1_3_or_out;
D1_3 = DFFE(D1_3_reg_input, GLOBAL(clk), , , );


--D1_4 is dsc:inst2|4 at LC52
D1_4_or_out = D1_3;
D1_4_reg_input = D1_4_or_out;
D1_4 = DFFE(D1_4_reg_input, GLOBAL(clk), , , );


--D1_5 is dsc:inst2|5 at LC50
D1_5_or_out = D1_4;
D1_5_reg_input = D1_5_or_out;
D1_5 = DFFE(D1_5_reg_input, GLOBAL(clk), , , );


--D1_6 is dsc:inst2|6 at LC49
D1_6_or_out = D1_5;
D1_6_reg_input = D1_6_or_out;
D1_6 = DFFE(D1_6_reg_input, GLOBAL(clk), , , );


--D1_7 is dsc:inst2|7 at LC1
D1_7_or_out = D1_6;
D1_7_reg_input = D1_7_or_out;
D1_7 = DFFE(D1_7_reg_input, GLOBAL(clk), , , );


--D1_9 is dsc:inst2|9 at LC51
D1_9_p2_out = D1_5 & !D1_7;
D1_9_p3_out = !D1_5 & D1_7;
D1_9_or_out = D1_9_p2_out # D1_9_p3_out;
D1_9_reg_input = D1_1 $ D1_9_or_out;
D1_9 = DFFE(D1_9_reg_input, GLOBAL(clk), , , );


--clk is clk at Pin_83
--operation mode is input

clk = INPUT();


--nrz is nrz at Pin_37
--operation mode is output

nrz = OUTPUT(B1_5);


--scout is scout at Pin_39
--operation mode is output

scout = OUTPUT(C1_12);


--dscout is dscout at Pin_40
--operation mode is output

dscout = OUTPUT(D1_9);