sc-dsc.map.rpt

数字通信系统的设计及其性能和所传输的数字信号的统计特性有关。所谓 加扰技术

Analysis & Synthesis report for SC-DSC compilation.
Fri Jun 01 14:01:29 2007
Version 3.0 Build 199 06/26/2003 SJ Full Version

Command: quartus_map --import_settings_files=on --export_settings_files=off sc-dsc -c SC-DSC



---------------------
; Table of Contents ;
---------------------
   1. Legal Notice
   2. Flow Summary
   3. Flow Settings
   4. Flow Elapsed Time
   5. Analysis & Synthesis Summary
   6. Analysis & Synthesis Settings
   7. Hierarchy
   8. Analysis & Synthesis Resource Utilization by Entity
   9. Analysis & Synthesis Equations
  10. Analysis & Synthesis Messages


----------------
; Legal Notice ;
----------------
Copyright (C) 1991-2003 Altera Corporation
Any  megafunction  design,  and related netlist (encrypted  or  decrypted),
support information,  device programming or simulation file,  and any other
associated  documentation or information  provided by  Altera  or a partner
under  Altera's   Megafunction   Partnership   Program  may  be  used  only
to program  PLD  devices (but not masked  PLD  devices) from  Altera.   Any
other  use  of such  megafunction  design,  netlist,  support  information,
device programming or simulation file,  or any other  related documentation
or information  is prohibited  for  any  other purpose,  including, but not
limited to  modification,  reverse engineering,  de-compiling, or use  with
any other  silicon devices,  unless such use is  explicitly  licensed under
a separate agreement with  Altera  or a megafunction partner.  Title to the
intellectual property,  including patents,  copyrights,  trademarks,  trade
secrets,  or maskworks,  embodied in any such megafunction design, netlist,
support  information,  device programming or simulation file,  or any other
related documentation or information provided by  Altera  or a megafunction
partner, remains with Altera, the megafunction partner, or their respective
licensors. No other licenses, including any licenses needed under any third
party's intellectual property, are provided herein.



-----------------------------------------------------------------
; Flow Summary                                                  ;
-----------------------------------------------------------------
; Flow Status           ; Successful - Fri Jun 01 14:01:29 2007 ;
; Compiler Setting Name ; SC-DSC                                ;
; Top-level Entity Name ; SC-DSC                                ;
; Family                ; MAX7000S                              ;
; Device                ; EPM7128SLC84-15                       ;
; Total macrocells      ; 17                                    ;
; Total pins            ; 4                                     ;
-----------------------------------------------------------------


-----------------------------------------------
; Flow Settings                               ;
-----------------------------------------------
; Option                ; Setting             ;
-----------------------------------------------
; Start date & time     ; 06/01/2007 14:01:29 ;
; Main task             ; Compilation         ;
; Compiler Setting Name ; SC-DSC              ;
-----------------------------------------------


---------------------------------------
; Flow Elapsed Time                   ;
---------------------------------------
; Module Name          ; Elapsed Time ;
---------------------------------------
; Analysis & Synthesis ; 00:00:01     ;
; Total                ; 00:00:01     ;
---------------------------------------


-----------------------------------------------------------------------
; Analysis & Synthesis Summary                                        ;
-----------------------------------------------------------------------
; Analysis & Synthesis Status ; Successful - Fri Jun 01 14:01:29 2007 ;
; Compiler Setting Name       ; SC-DSC                                ;
; Top-level Entity Name       ; SC-DSC                                ;
; Family                      ; MAX7000S                              ;
; Total macrocells            ; 17                                    ;
; Total pins                  ; 4                                     ;
-----------------------------------------------------------------------


------------------------------------------------------------
; Analysis & Synthesis Settings                            ;
------------------------------------------------------------
; Option                                        ; Setting  ;
------------------------------------------------------------
; Use Generated Physical Constraints File       ; On       ;
; Physical Synthesis Level for Resynthesis      ; Normal   ;
; Resynthesis Optimization Effort               ; Normal   ;
; Type of Retiming Performed During Resynthesis ; Full     ;
; Focus entity name                             ; |SC-DSC  ;
; Family name                                   ; MAX7000S ;
; Preserve fewer node names                     ; On       ;
; Disk space/compilation speed tradeoff         ; Normal   ;
------------------------------------------------------------


--------------
; Hierarchy  ;
--------------
Hierarchy
  SC-DSC
    nrz:inst
    SC:inst1
    dsc:inst2


------------------------------------------------------------------------
; Analysis & Synthesis Resource Utilization by Entity                  ;
------------------------------------------------------------------------
; Compilation Hierarchy Node ; Macrocells ; Pins ; Full Hierarchy Name ;
------------------------------------------------------------------------
; |SC-DSC                    ; 17         ; 4    ; |SC-DSC             ;
;    |SC:inst1|              ; 6          ; 0    ; |SC-DSC|SC:inst1    ;
;    |dsc:inst2|             ; 7          ; 0    ; |SC-DSC|dsc:inst2   ;
;    |nrz:inst|              ; 4          ; 0    ; |SC-DSC|nrz:inst    ;
------------------------------------------------------------------------


-----------------------------------
; Analysis & Synthesis Equations  ;
-----------------------------------
The equations can be found in E:\3 实验 扰码与解扰（用Quartus II)\SC\SC-DSC.map.eqn.


----------------------------------
; Analysis & Synthesis Messages  ;
----------------------------------
Info: *******************************************************************
Info: Running Quartus II Analysis & Synthesis
  Info: Version 3.0 Build 199 06/26/2003 SJ Full Version
  Info: Processing started: Fri Jun 01 14:01:28 2007
Info: Command: quartus_map --import_settings_files=on --export_settings_files=off sc-dsc -c SC-DSC
Info: Found 1 design units and 1 entities in source file E:\3 实验 扰码与解扰（用Quartus II)\SC\SC-DSC.bdf
  Info: Found entity 1: SC-DSC
Info: Found 1 design units and 1 entities in source file E:\3 实验 扰码与解扰（用Quartus II)\SC\nrz.bdf
  Info: Found entity 1: nrz
Info: Found 1 design units and 1 entities in source file E:\3 实验 扰码与解扰（用Quartus II)\SC\SC.gdf
  Info: Found entity 1: SC
Info: Found 1 design units and 1 entities in source file E:\3 实验 扰码与解扰（用Quartus II)\SC\dsc.bdf
  Info: Found entity 1: dsc
Info: Inferred 0 megafunctions from design logic
Info: Implemented 21 device resources after synthesis - the final resource count might be different
  Info: Implemented 1 input pins
  Info: Implemented 3 output pins
  Info: Implemented 17 macrocells
Info: Quartus II Analysis & Synthesis was successful. 0 errors, 0 warnings
  Info: Processing ended: Fri Jun 01 14:01:29 2007
  Info: Elapsed time: 00:00:01
Info: Writing report file SC-DSC.map.rpt