📄 sc-dsc.tan.rpt
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; Worst-case tco ; N/A ; None ; 8.000 ns ; nrz:inst|5 ; nrz ;
; Worst-case minimum tco ; N/A ; None ; 8.000 ns ; nrz:inst|5 ; nrz ;
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; Clock Setup: 'clk' ;
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; Slack ; Actual fmax (period) ; Source Name ; Destination Name ; Source Clock Name ; Destination Clock Name ; Required Setup Relationship ; Required Longest P2P Time ; Actual Longest P2P Time ;
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; N/A ; 76.92 MHz ( period = 13.000 ns ) ; dsc:inst2|1 ; dsc:inst2|9 ; clk ; clk ; None ; None ; None ;
; N/A ; 76.92 MHz ( period = 13.000 ns ) ; dsc:inst2|5 ; dsc:inst2|9 ; clk ; clk ; None ; None ; None ;
; N/A ; 76.92 MHz ( period = 13.000 ns ) ; dsc:inst2|7 ; dsc:inst2|9 ; clk ; clk ; None ; None ; None ;
; N/A ; 76.92 MHz ( period = 13.000 ns ) ; dsc:inst2|6 ; dsc:inst2|7 ; clk ; clk ; None ; None ; None ;
; N/A ; 76.92 MHz ( period = 13.000 ns ) ; dsc:inst2|5 ; dsc:inst2|6 ; clk ; clk ; None ; None ; None ;
; N/A ; 76.92 MHz ( period = 13.000 ns ) ; dsc:inst2|4 ; dsc:inst2|5 ; clk ; clk ; None ; None ; None ;
; N/A ; 76.92 MHz ( period = 13.000 ns ) ; dsc:inst2|3 ; dsc:inst2|4 ; clk ; clk ; None ; None ; None ;
; N/A ; 76.92 MHz ( period = 13.000 ns ) ; dsc:inst2|1 ; dsc:inst2|3 ; clk ; clk ; None ; None ; None ;
; N/A ; 76.92 MHz ( period = 13.000 ns ) ; SC:inst1|12 ; dsc:inst2|1 ; clk ; clk ; None ; None ; None ;
; N/A ; 76.92 MHz ( period = 13.000 ns ) ; SC:inst1|8 ; SC:inst1|9 ; clk ; clk ; None ; None ; None ;
; N/A ; 76.92 MHz ( period = 13.000 ns ) ; SC:inst1|9 ; SC:inst1|10 ; clk ; clk ; None ; None ; None ;
; N/A ; 76.92 MHz ( period = 13.000 ns ) ; SC:inst1|10 ; SC:inst1|11 ; clk ; clk ; None ; None ; None ;
; N/A ; 76.92 MHz ( period = 13.000 ns ) ; SC:inst1|11 ; SC:inst1|12 ; clk ; clk ; None ; None ; None ;
; N/A ; 76.92 MHz ( period = 13.000 ns ) ; SC:inst1|17 ; SC:inst1|8 ; clk ; clk ; None ; None ; None ;
; N/A ; 76.92 MHz ( period = 13.000 ns ) ; SC:inst1|12 ; SC:inst1|8 ; clk ; clk ; None ; None ; None ;
; N/A ; 76.92 MHz ( period = 13.000 ns ) ; SC:inst1|10 ; SC:inst1|8 ; clk ; clk ; None ; None ; None ;
; N/A ; 76.92 MHz ( period = 13.000 ns ) ; nrz:inst|5 ; SC:inst1|17 ; clk ; clk ; None ; None ; None ;
; N/A ; 76.92 MHz ( period = 13.000 ns ) ; nrz:inst|14 ; nrz:inst|3 ; clk ; clk ; None ; None ; None ;
; N/A ; 76.92 MHz ( period = 13.000 ns ) ; nrz:inst|3 ; nrz:inst|4 ; clk ; clk ; None ; None ; None ;
; N/A ; 76.92 MHz ( period = 13.000 ns ) ; nrz:inst|4 ; nrz:inst|5 ; clk ; clk ; None ; None ; None ;
; N/A ; 76.92 MHz ( period = 13.000 ns ) ; nrz:inst|14 ; nrz:inst|14 ; clk ; clk ; None ; None ; None ;
; N/A ; 76.92 MHz ( period = 13.000 ns ) ; nrz:inst|5 ; nrz:inst|14 ; clk ; clk ; None ; None ; None ;
; N/A ; 76.92 MHz ( period = 13.000 ns ) ; nrz:inst|4 ; nrz:inst|14 ; clk ; clk ; None ; None ; None ;
; N/A ; 76.92 MHz ( period = 13.000 ns ) ; nrz:inst|3 ; nrz:inst|14 ; clk ; clk ; None ; None ; None ;
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; tco ;
------------------------------------------------------------------------------------------
; Slack ; Required tco ; Actual tco ; Source Name ; Destination Name ; Source Clock Name ;
------------------------------------------------------------------------------------------
; N/A ; None ; 8.000 ns ; dsc:inst2|9 ; dscout ; clk ;
; N/A ; None ; 8.000 ns ; SC:inst1|12 ; scout ; clk ;
; N/A ; None ; 8.000 ns ; nrz:inst|5 ; nrz ; clk ;
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; Minimum tco ;
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; Minimum Slack ; Required Min tco ; Actual Min tco ; Source Name ; Destination Name ; Source Clock Name ;
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; N/A ; None ; 8.000 ns ; nrz:inst|5 ; nrz ; clk ;
; N/A ; None ; 8.000 ns ; SC:inst1|12 ; scout ; clk ;
; N/A ; None ; 8.000 ns ; dsc:inst2|9 ; dscout ; clk ;
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-----------------------------
; Timing Analyzer Messages ;
-----------------------------
Info: *******************************************************************
Info: Running Quartus II Timing Analyzer
Info: Version 3.0 Build 199 06/26/2003 SJ Full Version
Info: Processing started: Fri Jun 01 14:01:36 2007
Info: Command: quartus_tan --import_settings_files=off --export_settings_files=off sc-dsc -c SC-DSC
Warning: Found pins functioning as undefined clocks and/or memory enables
Info: Assuming node clk is an undefined clock
Info: Clock clk has Internal fmax of 76.92 MHz between source register dsc:inst2|1 and destination register dsc:inst2|9 (period= 13.0 ns)
Info: + Longest register to register delay is 8.000 ns
Info: 1: + IC(0.000 ns) + CELL(0.000 ns) = 0.000 ns; Loc. = LC55; REG Node = 'dsc:inst2|1'
Info: 2: + IC(2.000 ns) + CELL(6.000 ns) = 8.000 ns; Loc. = LC51; REG Node = 'dsc:inst2|9'
Info: Total cell delay = 6.000 ns
Info: Total interconnect delay = 2.000 ns
Info: - Smallest clock skew is 0.000 ns
Info: + Shortest clock path from clock clk to destination register is 3.000 ns
Info: 1: + IC(0.000 ns) + CELL(3.000 ns) = 3.000 ns; Loc. = Pin_83; CLK Node = 'clk'
Info: 2: + IC(0.000 ns) + CELL(0.000 ns) = 3.000 ns; Loc. = LC51; REG Node = 'dsc:inst2|9'
Info: Total cell delay = 3.000 ns
Info: - Longest clock path from clock clk to source register is 3.000 ns
Info: 1: + IC(0.000 ns) + CELL(3.000 ns) = 3.000 ns; Loc. = Pin_83; CLK Node = 'clk'
Info: 2: + IC(0.000 ns) + CELL(0.000 ns) = 3.000 ns; Loc. = LC55; REG Node = 'dsc:inst2|1'
Info: Total cell delay = 3.000 ns
Info: + Micro clock to output delay of source is 1.000 ns
Info: + Micro setup delay of destination is 4.000 ns
Info: tco from clock clk to destination pin dscout through register dsc:inst2|9 is 8.000 ns
Info: + Longest clock path from clock clk to source register is 3.000 ns
Info: 1: + IC(0.000 ns) + CELL(3.000 ns) = 3.000 ns; Loc. = Pin_83; CLK Node = 'clk'
Info: 2: + IC(0.000 ns) + CELL(0.000 ns) = 3.000 ns; Loc. = LC51; REG Node = 'dsc:inst2|9'
Info: Total cell delay = 3.000 ns
Info: + Micro clock to output delay of source is 1.000 ns
Info: + Longest register to pin delay is 4.000 ns
Info: 1: + IC(0.000 ns) + CELL(0.000 ns) = 0.000 ns; Loc. = LC51; REG Node = 'dsc:inst2|9'
Info: 2: + IC(0.000 ns) + CELL(4.000 ns) = 4.000 ns; Loc. = Pin_40; PIN Node = 'dscout'
Info: Total cell delay = 4.000 ns
Info: Minimum tco from clock clk to destination pin nrz through register nrz:inst|5 is 8.000 ns
Info: + Shortest clock path from clock clk to source register is 3.000 ns
Info: 1: + IC(0.000 ns) + CELL(3.000 ns) = 3.000 ns; Loc. = Pin_83; CLK Node = 'clk'
Info: 2: + IC(0.000 ns) + CELL(0.000 ns) = 3.000 ns; Loc. = LC56; REG Node = 'nrz:inst|5'
Info: Total cell delay = 3.000 ns
Info: + Micro clock to output delay of source is 1.000 ns
Info: + Shortest register to pin delay is 4.000 ns
Info: 1: + IC(0.000 ns) + CELL(0.000 ns) = 0.000 ns; Loc. = LC56; REG Node = 'nrz:inst|5'
Info: 2: + IC(0.000 ns) + CELL(4.000 ns) = 4.000 ns; Loc. = Pin_37; PIN Node = 'nrz'
Info: Total cell delay = 4.000 ns
Info: Quartus II Timing Analyzer was successful. 0 errors, 1 warning
Info: Processing ended: Fri Jun 01 14:01:37 2007
Info: Elapsed time: 00:00:01
Info: Writing report file SC-DSC.tan.rpt
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