sc-dsc.tan.rpt

数字通信系统的设计及其性能和所传输的数字信号的统计特性有关。所谓 加扰技术

Timing Analyzer report for SC-DSC compilation.
Fri Jun 01 14:01:37 2007
Version 3.0 Build 199 06/26/2003 SJ Full Version

Command: quartus_tan --import_settings_files=off --export_settings_files=off sc-dsc -c SC-DSC



---------------------
; Table of Contents ;
---------------------
   1. Legal Notice
   2. Flow Summary
   3. Flow Settings
   4. Flow Elapsed Time
   5. Timing Analyzer Settings
   6. Timing Analyzer Summary
   7. Clock Setup: 'clk'
   8. tco
   9. Minimum tco
  10. Timing Analyzer Messages


----------------
; Legal Notice ;
----------------
Copyright (C) 1991-2003 Altera Corporation
Any  megafunction  design,  and related netlist (encrypted  or  decrypted),
support information,  device programming or simulation file,  and any other
associated  documentation or information  provided by  Altera  or a partner
under  Altera's   Megafunction   Partnership   Program  may  be  used  only
to program  PLD  devices (but not masked  PLD  devices) from  Altera.   Any
other  use  of such  megafunction  design,  netlist,  support  information,
device programming or simulation file,  or any other  related documentation
or information  is prohibited  for  any  other purpose,  including, but not
limited to  modification,  reverse engineering,  de-compiling, or use  with
any other  silicon devices,  unless such use is  explicitly  licensed under
a separate agreement with  Altera  or a megafunction partner.  Title to the
intellectual property,  including patents,  copyrights,  trademarks,  trade
secrets,  or maskworks,  embodied in any such megafunction design, netlist,
support  information,  device programming or simulation file,  or any other
related documentation or information provided by  Altera  or a megafunction
partner, remains with Altera, the megafunction partner, or their respective
licensors. No other licenses, including any licenses needed under any third
party's intellectual property, are provided herein.



-----------------------------------------------------------------
; Flow Summary                                                  ;
-----------------------------------------------------------------
; Flow Status           ; Successful - Fri Jun 01 14:01:34 2007 ;
; Compiler Setting Name ; SC-DSC                                ;
; Top-level Entity Name ; SC-DSC                                ;
; Family                ; MAX7000S                              ;
; Device                ; EPM7128SLC84-15                       ;
; Total macrocells      ; 17 / 128 ( 13 % )                     ;
; Total pins            ; 8 / 68 ( 11 % )                       ;
-----------------------------------------------------------------


-----------------------------------------------
; Flow Settings                               ;
-----------------------------------------------
; Option                ; Setting             ;
-----------------------------------------------
; Start date & time     ; 06/01/2007 14:01:29 ;
; Main task             ; Compilation         ;
; Compiler Setting Name ; SC-DSC              ;
-----------------------------------------------


---------------------------------------
; Flow Elapsed Time                   ;
---------------------------------------
; Module Name          ; Elapsed Time ;
---------------------------------------
; Analysis & Synthesis ; 00:00:01     ;
; Fitter               ; 00:00:00     ;
; Assembler            ; 00:00:00     ;
; Timing Analyzer      ; 00:00:01     ;
; Total                ; 00:00:02     ;
---------------------------------------


--------------------------------------------------------------------------------------------------------------------------------------------
; Timing Analyzer Settings                                                                                                                 ;
--------------------------------------------------------------------------------------------------------------------------------------------
; Assignment File ; Source Name ; Destination Name ; Option                                                           ; Setting            ;
--------------------------------------------------------------------------------------------------------------------------------------------
; sc-dsc.psf      ;             ;                  ; Include external delays to/from device pins in fmax calculations ; Off                ;
; sc-dsc.psf      ;             ;                  ; Run All Timing Analyses                                          ; Off                ;
; sc-dsc.psf      ;             ;                  ; Ignore user-defined clock settings                               ; Off                ;
; sc-dsc.psf      ;             ;                  ; Default hold multicycle                                          ; Same As Multicycle ;
; sc-dsc.psf      ;             ;                  ; Cut off feedback from I/O pins                                   ; On                 ;
; sc-dsc.psf      ;             ;                  ; Cut off clear and preset signal paths                            ; On                 ;
; sc-dsc.psf      ;             ;                  ; Cut off read during write signal paths                           ; On                 ;
; sc-dsc.psf      ;             ;                  ; Cut paths between unrelated clock domains                        ; On                 ;
; sc-dsc.psf      ;             ;                  ; Run Minimum Analysis                                             ; On                 ;
; sc-dsc.psf      ;             ;                  ; Use Minimum Timing Models                                        ; Off                ;
; sc-dsc.psf      ;             ;                  ; Number of paths to report                                        ; 200                ;
; sc-dsc.psf      ;             ;                  ; Number of destination nodes to report                            ; 10                 ;
; sc-dsc.psf      ;             ;                  ; Number of source nodes to report per destination node            ; 10                 ;
; sc-dsc.psf      ;             ;                  ; Maximum Strongly Connected Component loop size                   ; 50                 ;
;                 ;             ;                  ; Device name                                                      ; EPM7128SLC84-15    ;
--------------------------------------------------------------------------------------------------------------------------------------------


----------------------------------------------------------------------------------------------------------------------
; Timing Analyzer Summary                                                                                            ;
----------------------------------------------------------------------------------------------------------------------
; Type                   ; Slack ; Required Time ; Actual Time                      ; Source Name ; Destination Name ;
----------------------------------------------------------------------------------------------------------------------
; Clock Setup: 'clk'     ; N/A   ; None          ; 76.92 MHz ( period = 13.000 ns ) ; nrz:inst|3  ; nrz:inst|14      ;