initialization.asm

dynatic power management example code for BF5

#include <defBF533.h>
#include "startup.h"

/************************************************************************************************/
/*			   GLOBAL & EXTERNAL DECLARATIONS													*/	
/************************************************************************************************/    
.SECTION	data1;

.GLOBAL 	Configure_Flash;
.GLOBAL 	Configure_Flags;
.GLOBAL 	Configure_Interrupts;

.EXTERN		PFA_HANDLER;
.EXTERN		PFB_HANDLER;

.SECTION 	program;	
/************************************************************************
 * SETUP FLASH SO THAT WE HAVE ACCESS TO LEDs VIA THE FLASH				*
 ************************************************************************/
Configure_Flash:
	/* Initalize EBIU control registers. */	
	P0.H = hi(EBIU_AMBCTL0); P0.L = lo(EBIU_AMBCTL0);		
	P1.H = hi(EBIU_AMBCTL1); P1.L = lo(EBIU_AMBCTL1);		
	
	R0.H = 0x78B0; R0.L = 0x78B0;								
	[P0] = R0;
	[P1] = R0; SSYNC;
	
	P0.H = hi(EBIU_AMGCTL); P0.L = lo(EBIU_AMGCTL);	
	R0.L = W[P0];
	R1 = 0xF;
	R0 = R0| R1;
	W[P0] = R0.L; SSYNC;
	
// initialize flash A csio regs (port A and B)
    // clear data registers
	p1.h = hi(flashA_csio); p1.l = lo(flashA_csio) + portA_data_out;
	r0 = 0x0;
	w[p1] = r0;	ssync;
	
    // direction control registers
	p1.l = lo(flashA_csio) + portA_data_dir;
	r0 = 0xFFFF(Z);      // set dir=output
	w[p1] = r0;	ssync;
	
	RTS;
Configure_Flash.end: nop;

/************************************************************************
 * SETUP FLAGS TO ACCEPT PUSH-BUTTON INPUTS AS INTERRUPTS				*
 ************************************************************************/
Configure_Flags:
   p0.h = hi(FIO_INEN); p0.l = lo(FIO_INEN);
   r0 = 0x0300 (z);
   w[p0] = r0;					// PF8-9 input enable

   p0.l = lo(FIO_EDGE);
   w[p0] = r0;					// PF8-9 edge sensitive

   p0.l = lo(FIO_MASKA_D);
   r0 = 0x0100 (z);
   w[p0] = r0;					// PF8 Interrupt A

   p0.l = lo(FIO_MASKB_D);
   r0 = 0x0200 (z);
   w[p0] = r0;					// PF9 Interrupt B

   p0.l = lo(FIO_DIR);
   r0 = 0xFCFF (z);
   w[p0] = r0;					// All PFs But PF8-9 Are Outputs
   
   RTS;
Configure_Flags.end: nop;

/************************************************************************
 * ENABLE CORE INTERRUPTS AND SYSTEM INTERRUPTS							*
 ************************************************************************/
Configure_Interrupts:
   P0.H = hi(SIC_IAR0); P0.L = lo(SIC_IAR0);
   R0.H = 0x7777; R0.L = 0x7777; // Assign Unused Interrupts to Lowest Priority (0x7)
   [P0++] = R0;		// Write SIC_IAR0 - RTC, Errors, and PLL Wake-Up Interrupt
   [P0++] = R0;		// Write SIC_IAR1 - UART TX/RX, SPORTx TX/RX, SPI, PPI

   R0.L = 0x1777;			// Assign PFA Interrupt to IVG8
   R0.H = 0x7772;			// Assign PFB Interrupt to IVG9
   [P0] = R0;				// Write SIC_IAR2
	
   P0.H = hi(EVT8); P0.L = lo(EVT8);
   R0.h = PFA_HANDLER; R0.l = PFA_HANDLER;	// User-Assigned PFA Handler (Int8)
   [p0++] = R0;								// EVT8 = PFA_HANDLER
        
   R0.h = PFB_HANDLER; R0.l = PFB_HANDLER;	// User-Assigned PFB Handler (Int9)
   [p0] = R0;								// EVT9 = PFB_HANDLER
   
   p0.h = hi(SIC_IMASK); p0.l = lo(SIC_IMASK);
   r0.h = 0x18;						// Unmask PFA (Bit 19) and PFB (Bit 20) Interrupts
   r0.l = 0;
   [p0] = r0;						// Enable GPF Interrupt A and B.

   cli r1;							// Enable PFA and PFB in IMASK.
   bitset (r1, 8);					// IVG8  = PFA (SW4-5 - Core Voltage Changer)
   bitset (r1, 9);					// IVG9  = PFB (SW6-7 - Core Frequency Changer)
   sti r1;							// Globally Enable Interrupts

   RTS;
Configure_Interrupts.end: nop;