📄 drivers.c
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/**************************************************************
*Includes
**************************************************************/
#include <REG51F.H>
#include <stdio.h>
#include "simple_phy.h"
#include "pub_def.h"
#include "drivers.h"
#include "MC13192_regs.h"
#include "MC13192_hw_config.h"
#include "mcu_hw_config.h"
/**************************************************************
* Defines
**************************************************************/
#define AssertCE MC13192_CE = 0 /* Asserts the MC13192 CE pin */
#define DeAssertCE MC13192_CE = 1 /* Deasserts the MC13192 CE pin */
/**************************************************************
* Globals
**************************************************************/
rx_packet_t *drv_rx_packet;
cca_measurement_t drv_cca_reading;
__uint8__ irq_value = 0;
extern unsigned char rtx_mode;
__uint8__ a;
__uint8__ b;
/**************************************************************
* Interrupt: MC13192 initiated interrupt handler
* Parameters: none
* Return: The interrupt will RTI unless valid data is recvd.
* In this case a pd_data_indication function call-back
* will be executed first, followed by a RTI
**************************************************************/
void interrupt_request() interrupt 0
{
/* The vector is defined in vectortable.c */
volatile __uint16__ status_content; /* Result of the status register read. */
__uint8__ dataLength = 0; /* Data length for the RX packet */
status_content = drv_read_spi_1(STATUS_ADDR); /* Read the MC13192 status register. */
// a = ((__uint8__*)&status_content)[0]; /* MSB */
// b = ((__uint8__*)&status_content)[1]; /* LSB */
// printf("%c",a);
// printf("%c",b);
printf("success\n");
DeAssertRTXEN();
disable_MC13192_interrupts();
if(status_content == 0x0040)
{
printf("success\n");
rtx_mode = IDLE_MODE;
}
else
{
dataLength = (__uint8__) (drv_read_spi_1(RX_PKT_LEN) & 0x7F); /* Read received packet length register and mask off length bits */
rtx_mode = IDLE_MODE; /* set the rtx_state to idle */
drv_write_spi_1(T1_HI_ADDR, 0x8000); /* Disables TC1 and clears the IRQ. */
drv_write_spi_1(T1_LO_ADDR, 0x0000);
drv_rx_packet->dataLength = dataLength;
drv_rx_packet->status = SUCCESS;
if (drv_rx_packet->status == SUCCESS)
{
drv_read_rx_ram(drv_rx_packet); /* read data from MC13192, check status */
if ((drv_rx_packet->rx_data[0] == 'x') && (drv_rx_packet->rx_data[2] == 'y') && (drv_rx_packet->rx_data[4] == 'z'))
{
printf("%c",drv_rx_packet->rx_data[0]);
printf("%c",drv_rx_packet->rx_data[1]);
printf("%c",drv_rx_packet->rx_data[2]);
printf("%c",drv_rx_packet->rx_data[3]);
printf("%c",drv_rx_packet->rx_data[4]);
printf("%c",drv_rx_packet->rx_data[5]);
}
}
}
restore_MC13192_interrupts();
}
/**************************************************************
* Function: Wake the MC13192 from Hibernate/Doze mode
* Parameters: none
* Return:
**************************************************************/
void Wake_MC13192 (void)
{
MC13192_ATTN = 0; /* Assert ATTN */
MC13192_ATTN = 1; /* Deassert ATTN */
}
/**************************************************************
* Function: Deassert the MC13192 RTXEN pin (forces IC to idle)
* Parameters: none
* Return:
**************************************************************/
void DeAssertRTXEN(void)
{
MC13192_RTXEN = 0; /* Deassert RTXEN */
}
/**************************************************************
* Function: Assert the MC13192 RTXEN pin (initiates programmed cycle)
* Parameters: none
* Return:
**************************************************************/
void AssertRTXEN(void)
{
MC13192_RTXEN = 1; /* Assert RTXEN */
}
/**************************************************************
* Function: write 1 word to SPI
* Parameters: SPI address, the word
* Return:
**************************************************************/
void drv_write_spi_1(__uint8__ addr, __uint16__ content)
{
__uint8__ temp_value; /* Used to flush the SPI1D register during read */
disable_MC13192_interrupts(); /* Necessary to prevent double SPI access */
AssertCE; /* Enables MC13192 SPI */
temp_value = addr & 0x3F; /* Mask address, 6bit addr. Set write bit (i.e. 0). */
spi_write(temp_value); /* For this bit to be set, SPTED MUST be set. Now write content MSB */
temp_value = content >> 8; /* Write MSB */
spi_write(temp_value); /* For this bit to be set, SPTED MUST be set. Now write content LSB */
temp_value = content & 0x00FF; /* Write LSB */
spi_write(temp_value); /* For this bit to be set, SPTED MUST be set. Now read last of garbage */
DeAssertCE; /* Disables MC13192 SPI */
restore_MC13192_interrupts(); /* Restore MC13192 interrupt status */
}
/**************************************************************
* Function: read 1 word from SPI
* Parameters: SPI address
* Return: a word, w. w[0] is the MSB, w[1] is the LSB
**************************************************************/
__uint16__ drv_read_spi_1(__uint8__ addr)
{
__uint16__ w; /* w[0] is MSB, w[1] is LSB */
__uint8__ temp_value; /* Used to flush the SPI1D register during read */
disable_MC13192_interrupts(); /* Necessary to prevent double SPI access */
AssertCE; /* Enables MC13192 SPI */
temp_value = (addr & 0x3f) | 0x80; /* Mask address, 6bit addr, Set read bit. */
spi_write(temp_value); /* For this bit to be set, SPTED MUST be set */
((__uint8__*)&w)[0] = spi_read(); /* MSB */
((__uint8__*)&w)[1] = spi_read(); /* LSB */
DeAssertCE; /* Disables MC13192 SPI */
restore_MC13192_interrupts(); /* Restore MC13192 interrupt status */
return w;
}
/**************************************************************
* Function: disable MC13192 interrupts
* Parameters: none
* Return:
**************************************************************/
void disable_MC13192_interrupts(void)
{
EA = 0;
}
/**************************************************************
* Function: restore MC13192 interrupts to previous condition
* Parameters: none
* Return:
**************************************************************/
void restore_MC13192_interrupts(void)
{
EA = 1;
}
/**************************************************************
* Function: write a block of data to TX packet RAM (whichever is selected)
* Parameters: length length of the block of data in bytes
* *contents pointer to the data block
**************************************************************/
void drv_write_tx_ram(tx_packet_t *tx_pkt)
{
__uint8__ i, ibyte, temp_value; /* i, ibyte are counters. temp_value is used to flush the SPI1D register during read */
__uint16__ reg; /* TX packet length register value */
reg = drv_read_spi_1(TX_PKT_LEN); /* Read the TX packet length register contents */
reg = (0xFF80 & reg) | (tx_pkt->dataLength + 2); /* Mask out old length setting and update. Add 2 for CRC */
drv_write_spi_1(TX_PKT_LEN, reg); /* Update the TX packet length field */
disable_MC13192_interrupts(); /* Necessary to prevent double SPI access */
AssertCE; /* Enables MC13192 SPI */
temp_value = TX_PKT; /* SPI TX ram data register */
spi_write(temp_value); /* For this bit to be set, SPTED MUST be set. Now write content MSB */
ibyte = 0; /* Byte counter for *contents */
for (i=0; i<((tx_pkt->dataLength+1) >> 1); i++) /* Word loop. Round up. */
{
temp_value = tx_pkt->tx_data[ibyte + 1]; /* Write MSB */
spi_write(temp_value); /* For this bit to be set, SPTED MUST be set. Now write content LSB */
temp_value = tx_pkt->tx_data[ibyte]; /* Write LSB */
ibyte=ibyte+2; /* Increment byte counter */
spi_write(temp_value); /* For this bit to be set, SPTED MUST be set.*/
}
DeAssertCE; /* Disables MC13192 SPI */
restore_MC13192_interrupts(); /* Restore MC13192 interrupt status */
}
/**************************************************************
* Function: read a block of data from RX packet RAM (whichever is selected)
* Parameters: *length returned length of the block of data in bytes
* *contents pointer to the data block storage
**************************************************************/
int drv_read_rx_ram(rx_packet_t *rx_pkt)
{
__uint8__ i, ibyte, temp_value, temp_data; /* i, ibyte are counters. temp_value is used to flush the SPI1D register during read */
__uint8__ status=0; /* holder for the return value */
__uint16__ rx_length;
rx_length = drv_read_spi_1(RX_PKT_LEN); /* Read the RX packet length register contents */
rx_length &= 0x007F; /* Mask out all but the RX packet length */
/* MC13192 reports length with 2 CRC bytes, remove them. */
/* ShortPacket is also checked in RX_ISR */
if (rx_length >= 3)
{
rx_pkt->dataLength = rx_length - 2;
}
else
{
rx_pkt->dataLength = 0;
}
if ((rx_pkt->dataLength >= 1) && (rx_pkt->dataLength <= rx_pkt->maxDataLength)) /* If <3, the packet is garbage */
{
disable_MC13192_interrupts(); /* Necessary to prevent double SPI access */
AssertCE; /* Enables MC13192 SPI */
temp_value = RX_PKT | 0x80; /* SPI RX ram data register */
spi_write(temp_value); /* For this bit to be set, SPTED MUST be set.*/
spi_read();
spi_read();
ibyte = 0; /* Byte counter for *contents */
for (i=0; i<((rx_length-1)>>1); i++) /* Word loop. Round up. Deduct CRC. */
{
temp_data = spi_read(); /* For this bit to be set, SPTED MUST be set. Get MSB */
if ((ibyte+3)==rx_length) /* For a trailing garbage byte, just read and discard */
{
temp_value = temp_data; /* Discard */
}
else
{
rx_pkt->rx_data[ibyte+1] = temp_data; /* Read MSB */
}
rx_pkt->rx_data[ibyte] = spi_read(); /* Read LSB */
ibyte=ibyte+2; /* Increment byte counter */
}
DeAssertCE; /* Disables MC13192 SPI */
rx_pkt->status = SUCCESS;
restore_MC13192_interrupts(); /* Restore MC13192 interrupt status */
}
/* Check to see if a larger packet than desired is received. */
if (rx_pkt->dataLength > rx_pkt->maxDataLength)
rx_pkt->status = OVERFLOW;
return status;
}
//模拟SPI口写函数
void spi_write(unsigned char write_data)
{
unsigned char spi_shifter = write_data;
unsigned char i;
for(i=0;i<8;i++)
{
MC13192_SPSCK = 0;
if((spi_shifter & 0x80) == 0x80)
MC13192_MOSI = 1;
else
MC13192_MOSI = 0;
MC13192_SPSCK = 1;
spi_shifter = spi_shifter << 1;
}
MC13192_SPSCK = 0;
}
//模拟SPI口读函数
unsigned char spi_read(void)
{
unsigned char read_data = 0x00;
unsigned char i;
for(i=0;i<8;i++)
{
MC13192_SPSCK = 0;
MC13192_SPSCK = 1;
if(MC13192_MISO == 1)
read_data = read_data + 1;
if(i < 7)
read_data = read_data << 1;
}
MC13192_SPSCK = 0;
return(read_data);
}
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