📄 simple_phy.lst
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253 {
254 1 __uint16__ reg;
255 1 __uint8__ power;
256 1 rtx_mode = CCA_MODE; /* Write energy detect mode */
257 1 reg = drv_read_spi_1(MODE_ADDR);
258 1 reg &= 0xFFF8;
259 1 reg |= CCA_MODE;
260 1 drv_write_spi_1(MODE_ADDR, reg);
261 1 AssertRTXEN();
262 1 while (rtx_mode != IDLE_MODE) /* Wait for energy detect to complete */
263 1 {
264 2 // MCU_LOW_POWER_WHILE;
265 2 }
266 1 reg = (drv_read_spi_1(CCA_RESULT_ADDR) & 0xFF00);
267 1 power = (reg >> 8);
268 1 return power;
269 1 }
270
271 /**************************************************************
272 * Function: Report energy from last successful RX packet
273 * Parameters: none
274 * Return: energy
275 **************************************************************/
276 __uint8__ PLME_link_quality (void)
277 /* Note: Actual power returned is: -(power/2) */
278 /* Global calibration required for accuracy. */
279 {
280 1 __uint16__ reg;
281 1 __uint8__ power;
282 1 reg = drv_read_spi_1(CCA_RESULT_ADDR);
283 1 power = ((reg & 0xFF00) >> 8);
284 1 return power;
285 1 }
286
287 /**************************************************************
288 * Function: Get MC13192 timer value
289 * Parameters: none
290 * Return: timer value
291 **************************************************************/
292 __uint32__ PLME_get_time_request(void)
293 {
294 1 __uint32__ upperword, lowerword;
295 1 __uint32__ current_time;
296 1 upperword = drv_read_spi_1(TIMESTAMP_HI_ADDR);
297 1 lowerword = drv_read_spi_1(TIMESTAMP_LO_ADDR);
298 1 upperword &= TIMESTAMP_HI_MASK; /* Clears TS_HELD bit. */
299 1 current_time = (__uint32__) (upperword << 16) | lowerword;
300 1 return current_time;
301 1 }
C51 COMPILER V7.06 SIMPLE_PHY 09/18/2006 21:57:30 PAGE 6
302
303 /**************************************************************
304 * Function: Set MC13192 CLKo frequency
305 * Parameters: frequency value
306 * Return: status
307 **************************************************************/
308 int PLME_set_MC13192_clock_rate(__uint8__ freq)
309 {
310 1 volatile __uint16__ current_value;
311 1 current_value = drv_read_spi_1(CLKS_ADDR); /* Read register and re-write */
312 1 current_value &= 0xFFF8;
313 1 current_value |= freq;
314 1 drv_write_spi_1(CLKS_ADDR, current_value);
315 1 return SUCCESS;
316 1 }
317
318 /**************************************************************
319 * Function: Set MC13192 timer frequency
320 * Parameters: frequency value
321 * Return: status
322 **************************************************************/
323 int PLME_set_MC13192_tmr_prescale (__uint8__ freq)
324 {
325 1 volatile __uint16__ current_value;
326 1 current_value = drv_read_spi_1(PRESCALE_ADDR);
327 1 current_value &= 0xFFF8;
328 1 current_value |= freq;
329 1 drv_write_spi_1(PRESCALE_ADDR, current_value);
330 1 return SUCCESS;
331 1 }
332
333 /**************************************************************
334 * Function: Set MC13192 timer value (i.e. initialize)
335 * Parameters: timer value
336 * Return: none
337 **************************************************************/
338 void PLME_set_time_request(__uint32__ requested_time)
339 {
340 1 __uint16__ upperword, lowerword, mode2_reg_val;
341 1 /* Split 32 bit input into 2 16 bit values */
342 1 upperword = (__uint16__) (requested_time >> 16) & 0x000000FF;
343 1 lowerword = (__uint16__) requested_time & 0x0000FFFF;
344 1 /* Program Time1 comparator with the desired value */
345 1 drv_write_spi_1(T1_HI_ADDR, upperword);
346 1 drv_write_spi_1(T1_LO_ADDR, lowerword);
347 1 /* Get current state of the MODE2 MC13192 register */
348 1 mode2_reg_val = drv_read_spi_1(MODE2_ADDR);
349 1 /* Set the Tmr_load bit */
350 1 mode2_reg_val |= 0x8000;
351 1 /* Now write the value back to MC13192 register MODE2 */
352 1 drv_write_spi_1(MODE2_ADDR, mode2_reg_val);
353 1 /* Clear the tmr_load bit */
354 1 mode2_reg_val &= 0x7FFF;
355 1 /* Clr the tmr_load bit to prepare for next set_time_request. */
356 1 drv_write_spi_1(MODE2_ADDR, mode2_reg_val);
357 1 return;
358 1 }
359
360 /**************************************************************
361 * Function: Set MC13192 timer compare value
362 * Parameters: timer value
363 * Return: status
C51 COMPILER V7.06 SIMPLE_PHY 09/18/2006 21:57:30 PAGE 7
364 **************************************************************/
365 int PLME_enable_MC13192_timer1(__uint32__ counter_value)
366 {
367 1 /* Load the timeout value into T1 with Timer disabled. */
368 1 drv_write_spi_1(T1_HI_ADDR, (__uint16__) ((counter_value >> 16) & 0x000000FF) | 0x000080FF);
369 1 drv_write_spi_1(T1_LO_ADDR, (__uint16__) (counter_value & 0x0000FFFF));
370 1 /* Turn Timer1 mask on. */
371 1 drv_write_spi_1(T1_HI_ADDR, (__uint16__) ((counter_value >> 16) & 0x000000FF));
372 1 drv_write_spi_1(T1_LO_ADDR, (__uint16__) (counter_value & 0x0000FFFF));
373 1 return SUCCESS;
374 1 }
375
376 /**************************************************************
377 * Function: Disable MC13192 timer comparator TC1
378 * Parameters: none
379 * Return: status
380 **************************************************************/
381 int PLME_disable_MC13192_timer1(void)
382 {
383 1 /* Load the timeout value into T1 with Timer disabled. */
384 1 /* Clear Timer1 if in RX_MODE_WTO */
385 1 drv_write_spi_1(T1_HI_ADDR, 0x8000);
386 1 drv_write_spi_1(T1_LO_ADDR, 0x0000);
387 1 // irq_mask_reg = drv_read_spi_1(IRQ_MASK);
388 1 // irq_mask_reg &= ~TIMER1_IRQMASK_BIT;
389 1 // drv_write_spi_1(IRQ_MASK, irq_mask_reg);
390 1 return SUCCESS;
391 1 }
392
393 /**************************************************************
394 * Function: Indicate a MC13192 reset condition
395 * Parameters: none
396 * Return: none
397 **************************************************************/
398 void PLME_MC13192_reset_indication (void)
399 {
400 1 // MLME_MC13192_reset_indication();
401 1 }
402
403 /**************************************************************
404 * Function: Force the MC13192 into a soft reset condition
405 * Parameters: none
406 * Return: status
407 **************************************************************/
408 int PLME_MC13192_soft_reset(void)
409 {
410 1 drv_write_spi_1(RESET, 0x00);
411 1 return SUCCESS;
412 1 }
413
414 /**************************************************************
415 * Function: Adjust the MC13192s crystal trim value
416 * Parameters: trim
417 * Return: status
418 **************************************************************/
419 int PLME_MC13192_xtal_adjust(__int8__ trim_value)
420 {
421 1 __uint16__ reg;
422 1 __uint16__ reg_value;
423 1 reg_value = (trim_value << 8); /* Shift the req value into the higher half word */
424 1 reg = drv_read_spi_1(XTAL_ADJ_ADDR); /* Read the current value of XTAL Reg */
425 1 reg = ((reg & 0x00FF) | reg_value);
C51 COMPILER V7.06 SIMPLE_PHY 09/18/2006 21:57:30 PAGE 8
426 1 drv_write_spi_1(XTAL_ADJ_ADDR, reg);
427 1 return SUCCESS;
428 1 }
429
430 /**************************************************************
431 * Function: Adjust the MC13192s gain compensator
432 * Parameters: gain compensation
433 * Return: status
434 **************************************************************/
435 int PLME_MC13192_FE_gain_adjust(__int8__ gain_value)
436 {
437 1 __uint16__ reg;
438 1 reg = drv_read_spi_1(FEGAIN_ADDR); /* Read the current value of GAIN Reg */
439 1 reg = ((reg & 0xFF00) | gain_value);
440 1 drv_write_spi_1(FEGAIN_ADDR, reg);
441 1 return SUCCESS;
442 1 }
443
444 /**************************************************************
445 * Function: Adjust the MC13192s Output power
446 * Parameters: PA Output adjust
447 * Return: status
448 **************************************************************/
449 int PLME_MC13192_PA_output_adjust(__uint8__ requested_pa_value)
450 {
451 1 __uint16__ reg;
452 1 __uint8__ pa_value;
453 1 int status = SUCCESS;
454 1 switch (requested_pa_value)
455 1 {
456 2 case MAX_POWER: /* Sets the PA drive level and PA gain to MAX. */
457 2 pa_value = 0xFF;
458 2 break;
459 2 case MIN_POWER:
460 2 pa_value = 0x00; //Sets the PA drive level and PA gain to min.
461 2 break;
462 2 default:
463 2 if (requested_pa_value > 15)
464 2 {
465 3 return OVERFLOW;
466 3 }
467 2 else
468 2 {
469 3 pa_value = requested_pa_value;
470 3 }
471 2 break;
472 2 }
473 1
474 1 reg = drv_read_spi_1(PA_ADJUST_ADDR); /* Read the current value of GAIN Reg */
475 1 reg &= 0xFF00;
476 1
477 1 if ((requested_pa_value == MAX_POWER) || (requested_pa_value == MIN_POWER))
478 1 reg |= pa_value;
479 1 else {
480 2 reg |= ((pa_value << 4) | 0x000C);
481 2 }
482 1 drv_write_spi_1(PA_ADJUST_ADDR, reg);
483 1 return SUCCESS;
484 1 }
485
486 /**************************************************************
487 * Function: Returns the RFIC version number.
C51 COMPILER V7.06 SIMPLE_PHY 09/18/2006 21:57:30 PAGE 9
488 * Parameters: none
489 * Return: version number
490 **************************************************************/
491 __uint8__ PLME_get_rfic_version(void)
492 {
493 1 __uint16__ reg;
494 1 reg = drv_read_spi_1(VERSION_REG); /* Read the version register version[12:10] */
495 1 reg &= VERSION_MASK; /* Shift to generate accurate number */
496 1
497 1 reg = reg >> 10; /* Hard coded to shift */
498 1 return (__uint8__) reg;
499 1 }
500
MODULE INFORMATION: STATIC OVERLAYABLE
CODE SIZE = 1089 ----
CONSTANT SIZE = ---- ----
XDATA SIZE = ---- ----
PDATA SIZE = ---- ----
DATA SIZE = ---- 38
IDATA SIZE = ---- ----
BIT SIZE = ---- ----
END OF MODULE INFORMATION.
C51 COMPILATION COMPLETE. 0 WARNING(S), 0 ERROR(S)
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