📄 simple_phy.lst
字号:
C51 COMPILER V7.06 SIMPLE_PHY 09/18/2006 21:57:30 PAGE 1
C51 COMPILER V7.06, COMPILATION OF MODULE SIMPLE_PHY
OBJECT MODULE PLACED IN simple_phy.OBJ
COMPILER INVOKED BY: D:\Keil\C51\BIN\C51.EXE simple_phy.c BROWSE DEBUG OBJECTEXTEND
stmt level source
1 /**************************************************************
2 *Includes
3 **************************************************************/
4 #include <REG51F.H>
5 #include <stdio.h>
6 #include "MC13192_regs.h"
7 #include "MC13192_hw_config.h"
8 #include "pub_def.h"
9 #include "drivers.h"
10 #include "simple_phy.h"
11 #include "simple_mac.h"
12 #include "mcu_hw_config.h"
13
14 /**************************************************************
15 * Globals
16 **************************************************************/
17 extern rx_packet_t *drv_rx_packet;
18 extern unsigned char rtx_mode;
19
20 /**************************************************************
21 * Version string to put in NVM. Note! size limits
22 **************************************************************/
23
24 // Normally it shoud be enough to change the version numbers.
25 #define PHY_Version "1.00"
26 #define PHY_Label "SPHY "
27
28 //#pragma MESSAGE DISABLE C3303 // Warning C3303: Implicit concatenation of strings
29 //#pragma MESSAGE DISABLE C4200 // Warning C4200: Other segment than in previous declaration
30 //#pragma CONST_SEG BOOTLOADER_PHY_NV_DATA0
31
32 // DO NOT CHANGE OR REMOVE
33
34 // This string will be located in the NV RAM0 section.
35 // Note!! Check that item is location in the sequence as specified.
36 //const unsigned char SPHY_Version[47] = "PHY " PHY_Label " Ver " PHY_Version " Build: "__DATE__" "__TIME_
-_;
37
38 //#pragma CONST_SEG DEFAULT
39
40 /**************************************************************
41 * Function: Transmit data packet
42 * Parameters: packet pointer
43 * Return: status
44 **************************************************************/
45 int pd_data_request(tx_packet_t *packet)
46 {
47 1 if (rtx_mode == IDLE_MODE)
48 1 {
49 2 drv_write_tx_ram(packet); /* Load the data into packet RAM */
50 2 PLME_set_trx_state_request(TX_MODE); /* transmit it */
51 2 /* Wait for the state to return to idle. (finish transmitting) */
52 2
53 2 return SUCCESS;
54 2 }
C51 COMPILER V7.06 SIMPLE_PHY 09/18/2006 21:57:30 PAGE 2
55 1 else
56 1 {
57 2 return RX_ON;
58 2 }
59 1 }
60
61
62
63 /**************************************************************
64 * Function: Hibernate the MC13192 (very low current, no CLKO)
65 * Parameters: none
66 * Return: status
67 **************************************************************/
68 int PLME_hibernate_request(void)
69 {
70 1 __uint16__ current_value;
71 1 rtx_mode = HIBERNATE_MODE;
72 1 current_value = drv_read_spi_1(MODE2_ADDR); /* Read MC13192 Hiberate register. */
73 1 current_value &= 0xFFFC;
74 1 current_value |= 0x0002; /* Hiberate enable */
75 1 drv_write_spi_1(MODE2_ADDR, current_value); /* Write back to MC13192 to enable hibernate mode. */
76 1 return SUCCESS; /* Call back to MAC layer indicating success. */
77 1 }
78
79 /**************************************************************
80 * Function: Doze the MC13192 (Low current, CLKO <= 1MHz)
81 * Parameters: none
82 * Return: status
83 **************************************************************/
84 int PLME_doze_request(void)
85 {
86 1 __uint16__ current_value;
87 1 rtx_mode = DOZE_MODE;
88 1 current_value = drv_read_spi_1(MODE2_ADDR); /* Read MC13192 Doze register. */
89 1 current_value &= 0xFFFC;
90 1 current_value |= 0x0001; /* Doze (acoma) enable */
91 1 drv_write_spi_1(MODE2_ADDR, current_value); /* Write back to MC13192 to enable hibernate mode. */
92 1 return SUCCESS; /* Call back to MAC layer indicating success. */
93 1 }
94
95 /**************************************************************
96 * Function: Wake the MC13192 from Hibernate or Doze
97 * Parameters: none
98 * Return: status
99 **************************************************************/
100 int PLME_wake_request(void)
101 {
102 1 __uint16__ current_value;
103 1 Wake_MC13192(); /* Wake up the device */
104 1 while (rtx_mode != IDLE_MODE_ATTN)
105 1 {
106 2 // MCU_LOW_POWER_WHILE; /* Wait until ATTN */
107 2 }
108 1 current_value = drv_read_spi_1(MODE2_ADDR); /* Read MC13192 Hiberate/Doze register. */
109 1 current_value &= 0xFFFC; /* Hiberate and Doze disable */
110 1 drv_write_spi_1(MODE2_ADDR, current_value); /* Write back to MC13192 to disable hibernate and doze mode.
-*/
111 1 rtx_mode = IDLE_MODE;
112 1 return SUCCESS;
113 1 }
114
115 /**************************************************************
C51 COMPILER V7.06 SIMPLE_PHY 09/18/2006 21:57:30 PAGE 3
116 * Function: Set the MC13192 operating channel
117 * Parameters: channel number
118 * Return: status
119 **************************************************************/
120 int PLME_set_channel_request(__uint8__ ch)
121 {
122 1 switch (ch)
123 1 {
124 2 case 0x00:
125 2 drv_write_spi_1(LO1_IDIV_ADDR,0x0F95);
126 2 drv_write_spi_1(LO1_NUM_ADDR,0x5000);
127 2 break;
128 2 case 0x01:
129 2 drv_write_spi_1(LO1_IDIV_ADDR,0x0F95);
130 2 drv_write_spi_1(LO1_NUM_ADDR,0xA000);
131 2 break;
132 2 case 0x02:
133 2 drv_write_spi_1(LO1_IDIV_ADDR,0x0F95);
134 2 drv_write_spi_1(LO1_NUM_ADDR,0xF000);
135 2 break;
136 2 case 0x03:
137 2 drv_write_spi_1(LO1_IDIV_ADDR,0x0F96);
138 2 drv_write_spi_1(LO1_NUM_ADDR,0x4000);
139 2 break;
140 2 case 0x04:
141 2 drv_write_spi_1(LO1_IDIV_ADDR,0x0F96);
142 2 drv_write_spi_1(LO1_NUM_ADDR,0x9000);
143 2 break;
144 2 case 0x05:
145 2 drv_write_spi_1(LO1_IDIV_ADDR,0x0F96);
146 2 drv_write_spi_1(LO1_NUM_ADDR,0xE000);
147 2 break;
148 2 case 0x06:
149 2 drv_write_spi_1(LO1_IDIV_ADDR,0x0F97);
150 2 drv_write_spi_1(LO1_NUM_ADDR,0x3000);
151 2 break;
152 2 case 0x07:
153 2 drv_write_spi_1(LO1_IDIV_ADDR,0x0F97);
154 2 drv_write_spi_1(LO1_NUM_ADDR,0x8000);
155 2 break;
156 2 case 0x08:
157 2 drv_write_spi_1(LO1_IDIV_ADDR,0x0F97);
158 2 drv_write_spi_1(LO1_NUM_ADDR,0xD000);
159 2 break;
160 2 case 0x09:
161 2 drv_write_spi_1(LO1_IDIV_ADDR,0x0F98);
162 2 drv_write_spi_1(LO1_NUM_ADDR,0x2000);
163 2 break;
164 2 case 0x0A:
165 2 drv_write_spi_1(LO1_IDIV_ADDR,0x0F98);
166 2 drv_write_spi_1(LO1_NUM_ADDR,0x7000);
167 2 break;
168 2 case 0x0B:
169 2 drv_write_spi_1(LO1_IDIV_ADDR,0x0F98);
170 2 drv_write_spi_1(LO1_NUM_ADDR,0xC000);
171 2 break;
172 2 case 0x0C:
173 2 drv_write_spi_1(LO1_IDIV_ADDR,0x0F99);
174 2 drv_write_spi_1(LO1_NUM_ADDR,0x1000);
175 2 break;
176 2 case 0x0D:
177 2 drv_write_spi_1(LO1_IDIV_ADDR,0x0F99);
C51 COMPILER V7.06 SIMPLE_PHY 09/18/2006 21:57:30 PAGE 4
178 2 drv_write_spi_1(LO1_NUM_ADDR,0x6000);
179 2 break;
180 2 case 0x0E:
181 2 drv_write_spi_1(LO1_IDIV_ADDR,0x0F99);
182 2 drv_write_spi_1(LO1_NUM_ADDR,0xB000);
183 2 break;
184 2 case 0x0F:
185 2 drv_write_spi_1(LO1_IDIV_ADDR,0x0F9A);
186 2 drv_write_spi_1(LO1_NUM_ADDR,0x0000);
187 2 break;
188 2 default:
189 2 drv_write_spi_1(LO1_IDIV_ADDR,0x0F97);
190 2 drv_write_spi_1(LO1_NUM_ADDR,0xD000);
191 2 return ERROR;
192 2 }
193 1 return SUCCESS;
194 1 }
195
196 /**************************************************************
197 * Function: Set the MC13192 transceive operation
198 * Parameters: operational mode
199 * Return: status
200 **************************************************************/
201 int PLME_set_trx_state_request(__uint8__ req_mode)
202 {
203 1 __uint16__ reg;
204 1 // DeAssertRTXEN();
205 1 reg = drv_read_spi_1(MODE_ADDR);
206 1 reg &= 0xFFF8; /* Clear mode. */
207 1 switch (req_mode)
208 1 {
209 2 case IDLE_MODE: /* Write Idle */
210 2
211 2 reg |= IDLE_MODE;
212 2 rtx_mode = IDLE_MODE;
213 2 drv_write_spi_1(MODE_ADDR, reg);
214 2 break;
215 2
216 2 case RX_MODE: /* Write RX */
217 2
218 2 rtx_mode = RX_MODE;
219 2 reg |= RX_MODE;
220 2 drv_write_spi_1(MODE_ADDR, reg);
221 2 AssertRTXEN();
222 2 break;
223 2
224 2 case RX_MODE_WTO: /* Write RX, but set rtx_mode to timeout */
225 2
226 2 rtx_mode = RX_MODE_WTO;
227 2 reg |= RX_MODE;
228 2 drv_write_spi_1(MODE_ADDR, reg);
229 2 AssertRTXEN();
230 2 break;
231 2
232 2 case TX_MODE: /* Write Tx. Note: force LO lock not used */
233 2
234 2 reg |= TX_MODE;
235 2 rtx_mode = TX_MODE;
236 2 drv_write_spi_1(MODE_ADDR, reg);
237 2 AssertRTXEN();
238 2 break;
239 2 default:
C51 COMPILER V7.06 SIMPLE_PHY 09/18/2006 21:57:30 PAGE 5
240 2 return ERROR;
241 2 }
242 1 return SUCCESS;
243 1 }
244
245 /**************************************************************
246 * Function: Measure channel energy
247 * Parameters: none
248 * Return: energy
249 **************************************************************/
250 __uint8__ PLME_energy_detect (void)
251 /* Note: Actual power returned is: -(power/2) */
252 /* Global calibration required for accuracy. */
⌨️ 快捷键说明
复制代码
Ctrl + C
搜索代码
Ctrl + F
全屏模式
F11
切换主题
Ctrl + Shift + D
显示快捷键
?
增大字号
Ctrl + =
减小字号
Ctrl + -