68332.h

用于城市轨道交通开发的CBTR 的开发

#define	SIMCR		0xFFFFFA00	//SIM CONFIGGRUATION
#define	SIMTR		0xFFFFFA02	//FACTORY TEST	
#define	SYNCR		0xFFFFFA04	//CLOCK SYNTHESIZER CONTROL	
#define	RSR		0xFFFFFA06	//RESET STATUS , LOW BYTE USED , HIGH BYTE UNUSED
#define	SIMTRE		0xFFFFFA08	//MODULE TEST E

//this registers assigned to odd address, use move.b to visit!!!
#define	PORTE0		0xFFFFFA11	//PORTE DATA, LOW BYTE USED, USE MOVE.B TO VISIT
#define	PORTE1		0xFFFFFA13	//PORTE DATA
#define	DDRE		0xFFFFFA15	//PORTE DIRECTION	
#define	PEPAR		0xFFFFFA17	//PORTE PIN Assignmnet Register
#define	PORTF0		0xFFFFFA19	//Portf data, use MOVE.B to visit	
#define	PORTF1		0xFFFFFA1B	//Portf data
#define	DDRF		0xFFFFFA1D	//Portf direction
#define	PFPAR		0xFFFFFA1F	//Portf pin assignment register
#define	SYPCR		0xFFFFFA21	//system protection

#define	PICR		0xFFFFFA22	//Perirdic interrupt control
#define	PITR		0xFFFFFA24	//Periodic interrupt timer
#define	SWSR		0xFFFFFA27	//software watchdog service register

#define	PORTC		0xFFFFFA41	//portc data	
#define	CSPAR0		0xFFFFFA44	//chip select pin assignment register0
#define	CAPAR1		0xFFFFFA46	//chip select pin assignment register1
#define	CSBARBT		0xFFFFFA48	//chip select base address for boot rom       ---/csboot
#define	CSORBT		0xFFFFFA4A	//chip select option for for boot rom        ----/csboot
#define	CSBAR0		0xFFFFFA4C	//chip select base address for chip select 0 ---- cs0	
#define	CSOR0		0xFFFFFA4E	//chip select option for for chip select0    ---- cs0
#define	CSBAR1		0xFFFFFA50	//chip select base address for chip select 1 ---- cs1
#define	CSOR1		0xFFFFFA52	//chip select option for for chip select1    ---- cs1
#define	CSBAR2		0xFFFFFA54	//chip select base address for chip select 2 ---- cs2
#define	CSOR2		0xFFFFFA56	//chip select option for for chip select2    ---- cs2
#define	CSBAR3		0xFFFFFA58	//chip select base address for chip select 3 ---- cs3
#define	CSOR3		0xFFFFFA5A	//chip select option for for chip select3    ---- cs3
#define	CSBAR4		0xFFFFFA5C	//chip select base address for chip select 4 ---- cs4
#define	CSOR4		0xFFFFFA5E	//chip select option for for chip select4    ---- cs4
#define	CSBAR5		0xFFFFFA60	//chip select base address for chip select 5 ---- cs5
#define	CSOR5		0xFFFFFA62	//chip select option for for chip select5    ---- cs5
#define	CSBAR6		0xFFFFFA64	//chip select base address for chip select 6 ---- cs6
#define	CSOR6		0xFFFFFA66	//chip select option for for chip select6    ---- cs6
#define	CSBAR7		0xFFFFFA68	//chip select base address for chip select 7 ---- cs7
#define	CSOR7		0xFFFFFA6A	//chip select option for for chip select7    ---- cs7
#define	CSBAR8		0xFFFFFA6C	//chip select base address for chip select 8 ---- cs8
#define	CSOR8		0xFFFFFA6E	//chip select option for for chip select8    ---- cs8
#define	CSBAR9		0xFFFFFA70	//chip select base address for chip select 9 ---- cs9
#define	CSOR9		0xFFFFFA72	//chip select option for for chip select9    ---- cs9
#define	CSBAR10		0xFFFFFA74	//chip select base address for chip select 10 ---- cs10
#define	CSOR10		0xFFFFFA76	//chip select option for for chip select10    ---- cs10

#define	TRAMMCR		0xFFFFFB00		//TPURAM Module configuration register
#define	TRAMTST		0xFFFFFB02		//TPURAM test 
#define	TRAMBAR		0xFFFFFB04		//TPURAM base address and status register


#define	QSMCR		0xFFFFFC00		//QSM configuration
#define	QTEST		0xFFFFFC02		//QSM test
#define	QILR		0xFFFFFC04		//QSM interrupt level, high byte
#define	QIVR		0xFFFFFC05		//QSM interrupt vector,low byte
#define	SCCR0		0xFFFFFC08		//SCI control register0
#define	SCCR1		0xFFFFFC0A		//SCI control register1	
#define	SCSR		0xFFFFFC0C		//SCI status register
#define	SCDR		0xFFFFFC0E		//SCI data register
#define	PORTQS		0xFFFFFC15		//portqs data .LOW BYTE
#define	PQSPAR		0xFFFFFC16		//portqs pin assignment
#define	DDRQS		0xFFFFFC17		//portqs data direction
#define	SPCR0		0xFFFFFC18		//QSPI CONTROL
#define	SPCR1		0xFFFFFC1A		//QSPI CONTROL
#define	SPCR2		0xFFFFFC1C		//QSPI CONTROL
#define	SPCR3		0xFFFFFC1E
#define SPSR		0xFFFFFC1F
#define	RR0		0xFFFFFD00
#define	RR1		0xFFFFFD02
#define	RR2		0xFFFFFD04
#define	RR3		0xFFFFFD06
#define	RR4		0xFFFFFD08
#define	RR5		0xFFFFFD0A
#define	RR6		0xFFFFFD0C
#define	RR7		0xFFFFFD0E
#define	RR8		0xFFFFFD10
#define	RR9		0xFFFFFD12
#define	RRA		0xFFFFFD14
#define	RRB		0xFFFFFD16
#define	RRC		0xFFFFFD18
#define	RRD		0xFFFFFD1A
#define	RRE		0xFFFFFD1C
#define	RRF		0xFFFFFD1E		//QSPI RECEIVE DATA		
#define	TR0		0xFFFFFD20
#define	TR1		0xFFFFFD22
#define	TR2		0xFFFFFD24
#define	TR3		0xFFFFFD26
#define	TR4		0xFFFFFD28
#define	TR5		0xFFFFFD2A
#define	TR6		0xFFFFFD2C
#define	TR7		0xFFFFFD2E
#define	TR8		0xFFFFFD30
#define	TR9		0xFFFFFD32
#define	TRA		0xFFFFFD34
#define	TRB		0xFFFFFD36
#define	TRC		0xFFFFFD38
#define	TRD		0xFFFFFD3A
#define	TRE		0xFFFFFD3C
#define	TRF		0xFFFFFD3E		//QSPI SEND DATA
#define	CR0		0xFFFFFD40
#define	CR1		0xFFFFFD41
#define	CR2		0xFFFFFD42
#define	CR3		0xFFFFFD43
#define	CR4		0xFFFFFD44
#define	CR5		0xFFFFFD45
#define	CR6		0xFFFFFD46
#define	CR7		0xFFFFFD47
#define	CR8		0xFFFFFD48
#define	CR9		0xFFFFFD49
#define	CRA		0xFFFFFD4A
#define	CRB		0xFFFFFD4B
#define	CRC		0xFFFFFD4C
#define	CRD		0xFFFFFD4D
#define	CRE		0xFFFFFD4E
#define	CRF		0xFFFFFD4F		//QSPI COMMAND

#define		TPUMCR    	0xfffe00	//TPU Module Configuration Reg
#define		TTCR      	0xfffe02	// for test
#define		DSCR      	0xfffe04	// for develop
#define		DSSR      	0xfffe06	// for develop
#define		TICR      	0xfffe08	//TPU Interrupt Config. Reg
#define		CIER      	0xfffe0a	//TPU Ch. Interrupt Enable Reg
#define		CFSR0      	0xfffe0c 	//TPU Ch. Function Select Reg 0
#define		CFSR1      	0xfffe0e 	//TPU Ch. Function Select Reg 1
#define		CFSR2      	0xfffe10 	//TPU Ch. Function Select Reg 2
#define		CFSR3      	0xfffe12 	//TPU Ch. Function Select Reg 3
#define		HSQR0      	0xfffe14 	//TPU Host Sequence Register 0
#define		HSQR1      	0xfffe16	//TPU Host Sequence Register 1
#define		HSRR0      	0xfffe18 	//TPU Host Service Req. Reg 0
#define		HSRR1      	0xfffe1a 	//TPU Host Service Req. Reg 1
#define		CPR0      	0xfffe1c 	//TPU Channel Priority Reg 0
#define		CPR1      	0xfffe1e 	//TPU Channel Priority Reg 1
#define		CISR      	0xfffe20 	//Channel Interrupt Status Reg


#define		TPU_PRAM0      	0xffff00 	//Channel 0 Parameter RAM
#define		TPU_PRAM1      	0xffff10 	//Channel 1 Parameter RAM
#define		TPU_PRAM2      	0xffff20 	//Channel 2 Parameter RAM
#define		TPU_PRAM3      	0xffff30 	//Channel 3 Parameter RAM
#define		TPU_PRAM4      	0xffff40 	//Channel 4 Parameter RAM
#define		TPU_PRAM5      	0xffff50 	//Channel 5 Parameter RAM
#define		TPU_PRAM6      	0xffff60 	//Channel 6 Parameter RAM
#define		TPU_PRAM7      	0xffff70 	//Channel 7 Parameter RAM
#define		TPU_PRAM8      	0xffff80 	//Channel 8 Parameter RAM
#define		TPU_PRAM9      	0xffff90 	//Channel 9 Parameter RAM
#define		TPU_PRAM10     	0xffffA0 	//Channel 10 Parameter RAM
#define		TPU_PRAM11     	0xffffB0 	//Channel 11 Parameter RAM
#define		TPU_PRAM12     	0xffffC0 	//Channel 12 Parameter RAM
#define		TPU_PRAM13     	0xffffD0 	//Channel 13 Parameter RAM
#define		TPU_PRAM14    	0xffffE0 	//Channel 14 Parameter RAM
#define		TPU_PRAM15     	0xffffF0 	//Channel 15 Parameter RAM