landzo

【开源】线性CCD自适应性算法攻略

                                hc = TRUE;
                            }
                        }
                    }
                }
            }
        }


        if (mmc)
        {
            esdhc_info_ptr->CARD = ESDHC_CARD_MMC;
        }
        if (ceata)
        {
            esdhc_info_ptr->CARD = ESDHC_CARD_CEATA;
        }
        if (io)
        {
            esdhc_info_ptr->CARD = ESDHC_CARD_SDIO;
        }
        if (mem)
        {
            esdhc_info_ptr->CARD = ESDHC_CARD_SD;
            if (hc)
            {
                esdhc_info_ptr->CARD = ESDHC_CARD_SDHC;
            }
        }
        if (io && mem)
        {
            esdhc_info_ptr->CARD = ESDHC_CARD_SDCOMBO;
            if (hc)
            {
                esdhc_info_ptr->CARD = ESDHC_CARD_SDHCCOMBO;
            }
        }

        /* De-Init GPIO */
        PORTE_PCR(0) = 0 & (PORT_PCR_MUX(4) | PORT_PCR_PS_MASK | PORT_PCR_PE_MASK | PORT_PCR_DSE_MASK);    /* ESDHC.D1  */
        PORTE_PCR(1) = 0 & (PORT_PCR_MUX(4) | PORT_PCR_PS_MASK | PORT_PCR_PE_MASK | PORT_PCR_DSE_MASK);    /* ESDHC.D0  */
        PORTE_PCR(2) = 0 & (PORT_PCR_MUX(4) | PORT_PCR_DSE_MASK);                                          /* ESDHC.CLK */
        PORTE_PCR(3) = 0 & (PORT_PCR_MUX(4) | PORT_PCR_PS_MASK | PORT_PCR_PE_MASK | PORT_PCR_DSE_MASK);    /* ESDHC.CMD */
        PORTE_PCR(4) = 0 & (PORT_PCR_MUX(4) | PORT_PCR_PS_MASK | PORT_PCR_PE_MASK | PORT_PCR_DSE_MASK);    /* ESDHC.D3  */
        PORTE_PCR(5) = 0 & (PORT_PCR_MUX(4) | PORT_PCR_PS_MASK | PORT_PCR_PE_MASK | PORT_PCR_DSE_MASK);    /* ESDHC.D2  */

        /* Set the ESDHC default baud rate */
        //SDHC_set_baudrate (esdhc_init_ptr->CLOCK_SPEED, esdhc_init_ptr->BAUD_RATE);
        SDHC_set_baudrate (core_clk_khz * 1000, esdhc_init_ptr->BAUD_RATE);

        /* Init GPIO again */
        PORTE_PCR(0) = 0xFFFF & (PORT_PCR_MUX(4) | PORT_PCR_PS_MASK | PORT_PCR_PE_MASK | PORT_PCR_DSE_MASK);    /* ESDHC.D1  */
        PORTE_PCR(1) = 0xFFFF & (PORT_PCR_MUX(4) | PORT_PCR_PS_MASK | PORT_PCR_PE_MASK | PORT_PCR_DSE_MASK);    /* ESDHC.D0  */
        PORTE_PCR(2) = 0xFFFF & (PORT_PCR_MUX(4) | PORT_PCR_DSE_MASK);                                          /* ESDHC.CLK */
        PORTE_PCR(3) = 0xFFFF & (PORT_PCR_MUX(4) | PORT_PCR_PS_MASK | PORT_PCR_PE_MASK | PORT_PCR_DSE_MASK);    /* ESDHC.CMD */
        PORTE_PCR(4) = 0xFFFF & (PORT_PCR_MUX(4) | PORT_PCR_PS_MASK | PORT_PCR_PE_MASK | PORT_PCR_DSE_MASK);    /* ESDHC.D3  */
        PORTE_PCR(5) = 0xFFFF & (PORT_PCR_MUX(4) | PORT_PCR_PS_MASK | PORT_PCR_PE_MASK | PORT_PCR_DSE_MASK);    /* ESDHC.D2  */

        /* Enable clock gate to SDHC module */
        SIM_SCGC3 |= SIM_SCGC3_SDHC_MASK;

        break;
    case IO_IOCTL_ESDHC_SEND_COMMAND:
        val = SDHC_send_command ((ESDHC_COMMAND_STRUCT_PTR)param32_ptr);
        if (val > 0)
        {
            result = ESDHC_ERROR_COMMAND_FAILED;
        }
        if (val < 0)
        {
            result = ESDHC_ERROR_COMMAND_TIMEOUT;
        }
        break;
    case IO_IOCTL_ESDHC_GET_BAUDRATE:
        if (NULL == param32_ptr)
        {
            result = BRTOS_INVALID_PARAMETER;
        }
        else
        {
            /* Get actual baudrate */
            val = ((SDHC_SYSCTL & SDHC_SYSCTL_SDCLKFS_MASK) >> SDHC_SYSCTL_SDCLKFS_SHIFT) << 1;
            val *= ((SDHC_SYSCTL & SDHC_SYSCTL_DVS_MASK) >> SDHC_SYSCTL_DVS_SHIFT) + 1;
            //*param32_ptr = (uint32)((esdhc_init_ptr->CLOCK_SPEED) / val);
            *param32_ptr = (uint32)((core_clk_khz * 1000) / val);
        }
        break;
    case IO_IOCTL_ESDHC_SET_BAUDRATE:
        if (NULL == param32_ptr)
        {
            result = BRTOS_INVALID_PARAMETER;
        }
        else if (0 == (*param32_ptr))
        {
            result = BRTOS_INVALID_PARAMETER;
        }
        else
        {
            if (! SDHC_is_running())
            {
                /* De-Init GPIO */
                PORTE_PCR(0) = 0 & (PORT_PCR_MUX(4) | PORT_PCR_PS_MASK | PORT_PCR_PE_MASK | PORT_PCR_DSE_MASK);    /* ESDHC.D1  */
                PORTE_PCR(1) = 0 & (PORT_PCR_MUX(4) | PORT_PCR_PS_MASK | PORT_PCR_PE_MASK | PORT_PCR_DSE_MASK);    /* ESDHC.D0  */
                PORTE_PCR(2) = 0 & (PORT_PCR_MUX(4) | PORT_PCR_DSE_MASK);                                          /* ESDHC.CLK */
                PORTE_PCR(3) = 0 & (PORT_PCR_MUX(4) | PORT_PCR_PS_MASK | PORT_PCR_PE_MASK | PORT_PCR_DSE_MASK);    /* ESDHC.CMD */
                PORTE_PCR(4) = 0 & (PORT_PCR_MUX(4) | PORT_PCR_PS_MASK | PORT_PCR_PE_MASK | PORT_PCR_DSE_MASK);    /* ESDHC.D3  */
                PORTE_PCR(5) = 0 & (PORT_PCR_MUX(4) | PORT_PCR_PS_MASK | PORT_PCR_PE_MASK | PORT_PCR_DSE_MASK);    /* ESDHC.D2  */

                /* Set closest baudrate */
                //SDHC_set_baudrate (esdhc_init_ptr->CLOCK_SPEED, *param32_ptr);
                SDHC_set_baudrate (core_clk_khz * 1000, *param32_ptr);

                /* Init GPIO again */
                PORTE_PCR(0) = 0xFFFF & (PORT_PCR_MUX(4) | PORT_PCR_PS_MASK | PORT_PCR_PE_MASK | PORT_PCR_DSE_MASK);    /* ESDHC.D1  */
                PORTE_PCR(1) = 0xFFFF & (PORT_PCR_MUX(4) | PORT_PCR_PS_MASK | PORT_PCR_PE_MASK | PORT_PCR_DSE_MASK);    /* ESDHC.D0  */
                PORTE_PCR(2) = 0xFFFF & (PORT_PCR_MUX(4) | PORT_PCR_DSE_MASK);                                          /* ESDHC.CLK */
                PORTE_PCR(3) = 0xFFFF & (PORT_PCR_MUX(4) | PORT_PCR_PS_MASK | PORT_PCR_PE_MASK | PORT_PCR_DSE_MASK);    /* ESDHC.CMD */
                PORTE_PCR(4) = 0xFFFF & (PORT_PCR_MUX(4) | PORT_PCR_PS_MASK | PORT_PCR_PE_MASK | PORT_PCR_DSE_MASK);    /* ESDHC.D3  */
                PORTE_PCR(5) = 0xFFFF & (PORT_PCR_MUX(4) | PORT_PCR_PS_MASK | PORT_PCR_PE_MASK | PORT_PCR_DSE_MASK);    /* ESDHC.D2  */

                /* Enable clock gate to SDHC module */
                SIM_SCGC3 |= SIM_SCGC3_SDHC_MASK;
            }
            else
            {
                result = IO_ERROR_DEVICE_BUSY;
            }
        }
        break;
    case IO_IOCTL_ESDHC_GET_BLOCK_SIZE:
        if (NULL == param32_ptr)
        {
            result = BRTOS_INVALID_PARAMETER;
        }
        else
        {
            /* Get actual ESDHC block size */
            *param32_ptr = (SDHC_BLKATTR & SDHC_BLKATTR_BLKSIZE_MASK) >> SDHC_BLKATTR_BLKSIZE_SHIFT;
        }
        break;
    case IO_IOCTL_ESDHC_SET_BLOCK_SIZE:
        if (NULL == param32_ptr)
        {
            result = BRTOS_INVALID_PARAMETER;
        }
        else
        {
            /* Set actual ESDHC block size */
            if (! SDHC_is_running())
            {
                if (*param32_ptr > 0x0FFF)
                {
                    result = BRTOS_INVALID_PARAMETER;
                }
                else
                {
                    SDHC_BLKATTR &= (~ SDHC_BLKATTR_BLKSIZE_MASK);
                    SDHC_BLKATTR |= SDHC_BLKATTR_BLKSIZE(*param32_ptr);
                }
            }
            else
            {
                result = IO_ERROR_DEVICE_BUSY;
            }
        }
        break;
    case IO_IOCTL_ESDHC_GET_BUS_WIDTH:
        if (NULL == param32_ptr)
        {
            result = BRTOS_INVALID_PARAMETER;
        }
        else
        {
            /* Get actual ESDHC bus width */
            val = (SDHC_PROCTL & SDHC_PROCTL_DTW_MASK) >> SDHC_PROCTL_DTW_SHIFT;
            if (ESDHC_PROCTL_DTW_1BIT == val)
            {
                *param32_ptr = ESDHC_BUS_WIDTH_1BIT;
            }
            else if (ESDHC_PROCTL_DTW_4BIT == val)
            {
                *param32_ptr = ESDHC_BUS_WIDTH_4BIT;
            }
            else if (ESDHC_PROCTL_DTW_8BIT == val)
            {
                *param32_ptr = ESDHC_BUS_WIDTH_8BIT;
            }
            else
            {
                result = ESDHC_ERROR_INVALID_BUS_WIDTH;
            }
        }
        break;
    case IO_IOCTL_ESDHC_SET_BUS_WIDTH:
        if (NULL == param32_ptr)
        {
            result = BRTOS_INVALID_PARAMETER;
        }
        else
        {
            /* Set actual ESDHC bus width */
            if (! SDHC_is_running())
            {
                if (ESDHC_BUS_WIDTH_1BIT == *param32_ptr)
                {
                    SDHC_PROCTL &= (~ SDHC_PROCTL_DTW_MASK);
                    SDHC_PROCTL |= SDHC_PROCTL_DTW(ESDHC_PROCTL_DTW_1BIT);
                }
                else if (ESDHC_BUS_WIDTH_4BIT == *param32_ptr)
                {
                    SDHC_PROCTL &= (~ SDHC_PROCTL_DTW_MASK);
                    SDHC_PROCTL |= SDHC_PROCTL_DTW(ESDHC_PROCTL_DTW_4BIT);
                }
                else if (ESDHC_BUS_WIDTH_8BIT == *param32_ptr)
                {
                    SDHC_PROCTL &= (~ SDHC_PROCTL_DTW_MASK);
                    SDHC_PROCTL |= SDHC_PROCTL_DTW(ESDHC_PROCTL_DTW_8BIT);
                }
                else
                {
                    result = ESDHC_ERROR_INVALID_BUS_WIDTH;
                }
            }
            else
            {
                result = IO_ERROR_DEVICE_BUSY;
            }
        }
        break;
    case IO_IOCTL_ESDHC_GET_CARD:
        if (NULL == param32_ptr)
        {
            result = BRTOS_INVALID_PARAMETER;
        }
        else
        {
            /* 80 clocks to update levels */
            SDHC_SYSCTL |= SDHC_SYSCTL_INITA_MASK;
            while (SDHC_SYSCTL & SDHC_SYSCTL_INITA_MASK)
                { };

            /* Update and return actual card status */
            if (SDHC_IRQSTAT & SDHC_IRQSTAT_CRM_MASK)
            {
                SDHC_IRQSTAT |= SDHC_IRQSTAT_CRM_MASK;
                esdhc_info_ptr->CARD = ESDHC_CARD_NONE;
            }
            if (SDHC_PRSSTAT & SDHC_PRSSTAT_CINS_MASK)
            {
                if (ESDHC_CARD_NONE == esdhc_info_ptr->CARD)
                {
                    esdhc_info_ptr->CARD = ESDHC_CARD_UNKNOWN;
                }
            }
            else
            {
                esdhc_info_ptr->CARD = ESDHC_CARD_NONE;
            }
            *param32_ptr = esdhc_info_ptr->CARD;
        }
        break;
    case IO_IOCTL_DEVICE_IDENTIFY:
        /* Get ESDHC device parameters */
        param32_ptr[IO_IOCTL_ID_PHY_ELEMENT]  = IO_DEV_TYPE_PHYS_ESDHC;
        param32_ptr[IO_IOCTL_ID_LOG_ELEMENT]  = IO_DEV_TYPE_LOGICAL_MFS;
        param32_ptr[IO_IOCTL_ID_ATTR_ELEMENT] = IO_ESDHC_ATTRIBS;
        /*
        if (esdhc_fd_ptr->FLAGS & IO_O_RDONLY)
        {
            param32_ptr[IO_IOCTL_ID_ATTR_ELEMENT] &= (~ IO_DEV_ATTR_WRITE);
        }
        */
        break;
    case IO_IOCTL_FLUSH_OUTPUT:
        /* Wait for transfer complete */
        SDHC_status_wait (SDHC_IRQSTAT_TC_MASK);
        if (SDHC_IRQSTAT & (SDHC_IRQSTAT_DEBE_MASK | SDHC_IRQSTAT_DCE_MASK | SDHC_IRQSTAT_DTOE_MASK))
        {
            SDHC_IRQSTAT |= SDHC_IRQSTAT_DEBE_MASK | SDHC_IRQSTAT_DCE_MASK | SDHC_IRQSTAT_DTOE_MASK;
            result = ESDHC_ERROR_DATA_TRANSFER;
        }
        SDHC_IRQSTAT |= SDHC_IRQSTAT_TC_MASK | SDHC_IRQSTAT_BRR_MASK | SDHC_IRQSTAT_BWR_MASK;
        break;
    default:
        result = IO_ERROR_INVALID_IOCTL_CMD;
        break;
    }
    return result;
}