sl_x400p.c

OpenSS7 This the fourth public release of the OpenSS7 Master Package. See README in the release for

				xlb[offset] = 0x55;
			for (offset = 0x22; offset <= 0x25; offset++)
				xlb[offset] = 0xff;
			timeout = jiffies + 100 * HZ / 1000;
			while (jiffies < timeout) ;
		}

		xlb[0x1b] = 0x9a;	/* CRC3: set ESR as well */
		xlb[0x1b] = 0x82;	/* CRC3: TSCLKM only */
		break;
	}
	case V401PE:
	{
		u_char reg33, reg35, reg40, reg78, reg7a;

		/* There are three other synchronization modes: 0x00 TCLK only, 0x02 switch to RCLK 
		   if TCLK fails, 0x04 external clock, 0x06 loop.  And then 0x80 selects the
		   TSYSCLK pin instead of the MCLK pin when in external clock mode. */
		/* Hmmm. tor3 driver has TCLK only for T1, but RCLK if TCLK fails for E1! */
		xlb[0x70] = 0x02;	/* LOTCMC into TCSS0 */
		/* IOCR1.0=0 Output data format is bipolar, IOCR1.1=1 TSYNC is an output, IOCR1.4=1 
		   RSYNC is an input (elastic store). */
		xlb[0x01] = 0x12;	/* RSIO + 1 is from O12.0 */
		xlb[0x02] = 0x03;	/* RSYSCLK/TSYSCLK 8.192MHz IBO */
		xlb[0x4f] = 0x11;	/* RES/TES (elastic store) enabled */
#if 0
		/* We should really reset the elastic store after reset like so: */
		xlb[0x4f] = 0x55;	/* RES/TES (elastic store) reset */
		xlb[0x4f] = 0x11;	/* RES/TES (elastic store) enabled */
		/* And even align it like so: */
		xlb[0x4f] = 0x99;	/* RES/TES (elastic store) reset */
		xlb[0x4f] = 0x11;	/* RES/TES (elastic store) enabled */
#endif
		reg33 = 0x00;
		reg35 = 0x10;	/* TSiS */
		reg40 = 0x00;

		switch (sp->config.ifframing) {
		default:
			sp->config.ifframing = SDL_FRAMING_CCS;
		case SDL_FRAMING_CCS:
			reg40 |= 0x06;
			reg33 |= 0x40;
			break;
		case SDL_FRAMING_CAS:
			break;
		}
		switch (sp->config.ifcoding) {
		default:
			sp->config.ifcoding = SDL_CODING_HDB3;
		case SDL_CODING_HDB3:
			reg33 |= 0x20;
			reg35 |= 0x04;
			break;
		case SDL_CODING_AMI:
			break;
		}
		switch (sp->config.ifgcrc) {
		case SDL_GCRC_CRC4:
			reg33 |= 0x08;
			reg35 |= 0x01;
			break;
		default:
			break;
		}
		/* We could be setting automatic report alarm generation (0x01) (T1) or automatic
		   AIS generation (0x02) (E1). */
		xlb[0x35] = reg35;	/* TSiS, TCRC4 (from 014.4), THDB3 (from O14.6) */
		xlb[0x36] = 0x04;	/* AEBE 36.2 */
		xlb[0x34] = 0x01;	/* RCL (1ms) */
		xlb[0x40] = reg40;	/* RCCS, TCCS */
		xlb[0x33] = reg33 | 0x01;	/* RCR4, RHDB3, RSM, SYNCE, RESYNC */
		xlb[0x33] = reg33 | 0x00;	/* RCR4, RHDB3, RSM, SYNCE */
		/* This is a little peculiar: the host should be using Method 3 in section 22.3 of
		   the DS2155 manual instead of this method that only permits 250us to read or
		   write the bits. */
		xlb[0xd0] = 0x1b;	/* TAFR */
		xlb[0xd1] = 0x5f;	/* TNAFR */

		xlb[0x79] = 0x98;	/* JACLK on for E1 */
		xlb[0x7b] = 0x0f;	/* 120 Ohm term, MCLK 2.048 MHz */

		switch (cd->device) {
		case XP_DEV_DS2155:
			xlb[0x7d] = 0x00;	/* Automatic gain control */
			break;
		case XP_DEV_DS2156:
			/* DS2156 does not have Tx AGC register */
			break;
		}

		/* We use TX levels to determine LBO, impedance, CSU operation, or monitoring
		   operation.  During monitoring operation, the transmitters are powered off. */
		/* For E1, LBO is: 000XXXXX 75 Ohm normal 001XXXXX 120 Ohm normal 100XXXXX 75 Ohm
		   high return loss 101XXXXX 120 Ohm high return loss For T1, LBO is: 000XXXXX
		   DSX-1 ( 0ft - 133ft) / 0dB CSU 001XXXXX DSX-1 (133ft - 266ft) 010XXXXX DSX-1
		   (266ft - 399ft) 011XXXXX DSX-1 (399ft - 533ft) 100XXXXX DSX-1 (533ft - 666ft)
		   101XXXXX -7.5dB CSU 110XXXXX -15.0dB CSU 111XXXXX -22.5dB CSU txlevel 0000 TX on 
		   DSX-1 ( 0ft - 133ft) / 0dB CSU or 75 Ohm normal 0001 TX on DSX-1 (133ft - 266ft) 
		   or 120 Ohm normal 0010 TX on DSX-1 (266ft - 399ft) or (invalid) 0011 TX on DSX-1 
		   (399ft - 533ft) or (invalid) 0100 TX on DSX-1 (533ft - 666ft) or 75 Ohm high RL
		   0101 TX on -7.5dB CSU or 120 Ohm high RL 0110 TX on -15.0dB CSU or (invalid)
		   0111 TX on -22.5dB CSU or (invalid) 1000 TX off 0dB Gain monitoring mode 1001 TX 
		   off 20dB Gain monitoring mode 1010 TX off 26dB Gain monitoring mode 1011 TX off
		   32dB Gain monitoring mode 1100 (invalid) 1101 (invalid) 1110 (invalid) 1111
		   (invalid) */

		if (sp->config.iftxlevel < 8) {
			reg7a = 0x00;	/* no gain */
			reg78 = 0x31;	/* 120 Ohm normal, transmitter on, -43dB EGL */
			// reg78 |= ((sp->config.iftxlevel & 0x1) << 5); /* LBO */
		} else {
			/* monitoring mode */
			reg7a = 0x00;	/* no gain */
			reg78 = 0x30;	/* 120 Ohm normal, transmitter off, -43dB EGL */
			reg7a |= ((sp->config.iftxlevel & 0x3) << 3);	/* Linear gain */
		}
		// reg78 &= ~0x01; /* disable transmitter */

		xlb[0x78] = reg78;
		xlb[0x7a] = reg7a;
		break;
	}
	case V400PT:
	case T400P:
	case T400PSS7:
	{
		unsigned char val, reg09, reg7c;
		int japan = (cd->config.ifgtype == SDL_GTYPE_J1);

		xlb[0x2b] = 0x08;	/* Full-on sync required (RCR1) */
		xlb[0x2c] = 0x08;	/* RSYNC is an input (RCR2) */
		xlb[0x35] = 0x10;	/* RBS enable (TCR1) */
		xlb[0x36] = 0x04;	/* TSYNC to be output (TCR2) */
		xlb[0x37] = 0x9c;	/* Tx & Rx Elastic stor, sysclk(s) = 2.048 mhz, loopback
					   controls (CCR1) */

		xlb[0x12] = 0x22;	/* IBCC 5-bit loop up, 3-bit loop down code */
		xlb[0x13] = 0x80;	/* TCD - 10000 */
		xlb[0x14] = 0x80;	/* RUPCD - 10000 */
		xlb[0x15] = 0x80;	/* RDNCD - 100 */

		xlb[0x19] = japan ? 0x80 : 0x00;	/* set japanese mode, no local loop */
		xlb[0x1e] = japan ? 0x80 : 0x00;	/* set japanese mode, no local loop */

		/* Enable F bits pattern */
		switch (sp->config.ifframing) {
		default:
		case SDL_FRAMING_SF:
			val = 0x20;
			break;
		case SDL_FRAMING_ESF:
			val = 0x88;
			break;
		}
		switch (sp->config.ifcoding) {
		default:
		case SDL_CODING_AMI:
			break;
		case SDL_CODING_B8ZS:
			val |= 0x44;
			break;
		}
		xlb[0x38] = val;
		if (sp->config.ifcoding != SDL_CODING_B8ZS)
			xlb[0x7e] = 0x1c;	/* Set FDL register to 0x1c */
		if (sp->config.iftxlevel < 8) {
			/* not monitoring mode */
			reg09 = 0x00;	/* TEST2 no gain */
			reg7c = 0x00;	/* 0dB CSU, transmitters on */
			reg7c |= ((sp->config.iftxlevel & 0x7) << 5);	/* LBO */
		} else {
			/* monitoring mode */
			reg09 = 0x00;	/* TEST2 no gain */
			reg7c = 0x01;	/* 0dB CSU, transmitters off */
			switch (sp->config.iftxlevel & 0x3) {
			case 1:
				reg09 |= 0x72;	/* TEST2 12dB gain */
				break;
			case 2:
			case 3:
				reg09 |= 0x70;	/* TEST2 20db gain */
				break;
			}
		}
		// reg7c |= 0x01; /* disable trasnmitter */

		xlb[0x09] = reg09;
		xlb[0x7c] = reg7c;

#if 0
		if (timeouts) {
			xlb[0x0a] = 0x80;	/* LIRST to reset line interface */
			timeout = jiffies + 100 * HZ / 1000;
			while (jiffies < timeout) ;
		}
#endif
		xlb[0x0a] = 0x30;	/* LIRST bask to normal, Resetting elastic buffers */
		{
			int byte, c;
			unsigned short mask = 0;

			/* establish which channels are clear channel */
			for (c = 0; c < 24; c++) {
				int slot = xp_t1_chan_map[c];

				byte = c >> 3;
				if (!cd->spans[sp->span]->slots[slot]
				    || cd->spans[sp->span]->slots[slot]->sdl.config.
				    iftype != SDL_TYPE_DS0A)
					mask |= 1 << (c % 8);
				if ((c % 8) == 7) {
					xlb[0x39 + byte] = mask;
					mask = 0;
				}
			}
		}
		break;
	}
	case V401PT:
	{
		unsigned char reg04, reg05, reg06, reg07, reg78, reg7a;

		/* There are three other synchronization modes: 0x00 TCLK only, 0x02 switch to RCLK 
		   if TCLK fails, 0x04 external clock, 0x06 loop.  And then 0x80 selects the
		   TSYSCLK pin instead of the MCLK pin when in external clock mode. */
		/* Hmmm. tor3 driver has TCLK only for T1, but RCLK if TCLK fails for E1! */
		xlb[0x70] = 0x06;	/* LOTCMC into TCSS0 */
		/* IOCR1.0=0 Output data format is bipolar, IOCR1.1=1 TSYNC is an output, IOCR1.4=1 
		   RSYNC is an input (elastic store). */
		xlb[0x01] = 0x12;	/* RSIO + 1 is from O12.0 */
		xlb[0x02] = 0x03;	/* RSYSCLK/TSYSCLK 8.192MHz IBO */
		xlb[0x4f] = 0x11;	/* RES/TES (elastic store) enabled */
#if 0
		/* We should really reset the elastic store after reset like so: */
		xlb[0x4f] = 0x55;	/* RES/TES (elastic store) reset */
		xlb[0x4f] = 0x11;	/* RES/TES (elastic store) enabled */
		/* And even align it like so: */
		xlb[0x4f] = 0x99;	/* RES/TES (elastic store) reset */
		xlb[0x4f] = 0x11;	/* RES/TES (elastic store) enabled */
#endif
		xlb[0xb6] = 0x22;	/* IBCC 5-bit loop up, 3-bit loop down code */
		xlb[0xb7] = 0x80;	/* TCD1 - 10000 loop up code (for now) */
		xlb[0xb8] = 0x00;	/* TCD2 don't care */
		xlb[0xb9] = 0x80;	/* RUPCD1 - 10000 receive loop up code */
		xlb[0xba] = 0x00;	/* RUPCD2 don't care */
		xlb[0xbb] = 0x80;	/* RDNCD1 - 100 receive loop down code */
		xlb[0xbc] = 0x00;	/* RDNCD2 don't card */

		reg04 = 0x00;
		reg05 = 0x10;	/* TSSE */
		reg06 = 0x00;
		reg07 = 0x00;

		switch (sp->config.ifgcrc) {
		default:
			sp->config.ifgcrc = SDL_GCRC_CRC6;
		case SDL_GCRC_CRC6:
			break;
		case SDL_GCRC_CRC6J:
			reg04 |= 0x02;
			reg05 |= 0x80;
			break;
		}
		switch (sp->config.ifframing) {
		default:
			sp->config.ifframing = SDL_FRAMING_ESF;
		case SDL_FRAMING_ESF:
			reg04 |= 0x40;
			reg07 |= 0x04;
			break;
		case SDL_FRAMING_SF:	/* D4 */
			break;
		}
		switch (sp->config.ifcoding) {
		default:
			sp->config.ifcoding = SDL_CODING_B8ZS;
		case SDL_CODING_B8ZS:
			reg04 |= 0x20;
			reg06 |= 0x80;
			break;
		case SDL_CODING_AMI:
			break;
		}
		xlb[0x04] = reg04;	/* RESF RB8ZS RCRC6J */
		xlb[0x05] = reg05;	/* TSSE TCRC6J */
		xlb[0x06] = reg06;	/* TB8ZS */
		xlb[0x07] = reg07;	/* TESF */

#if 0
		xlb[0x03] = 0x08 | 0x01;	/* SYNCC/SYNCE, RESYNC */
		xlb[0x03] = 0x08 | 0x00;	/* SYNCC/SYNCE */
#endif

		xlb[0x40] = 0x00;	/* RCCS, TCCS set to zero for T1 */

#if 0
		if (timeouts) {
			xlb[0x79] = 0x58;	/* JACLK on for T1 (and reset) */
			timeout = jiffies + 100 * HZ / 1000;
			while (jiffies < timeout) ;
		}
#endif
		xlb[0x79] = 0x18;	/* JACLK on for T1 */

		switch (cd->device) {
		case XP_DEV_DS2155:
			xlb[0x7d] = 0x00;	/* Automatic gain control */
			break;
		case XP_DEV_DS2156:
			/* DS2156 does not have Tx AGC register */
			break;
		}

		if (sp->config.iftxlevel < 8) {
			reg7a = 0x00;	/* no gain */
			reg78 = 0x01;	/* 0dB CSU, trasnmitter on, -36dB EGL */
			reg78 |= ((sp->config.iftxlevel & 0x7) << 5);	/* LBO */
		} else {
			/* monitoring mode */
			reg7a = 0x00;	/* no gain */
			reg78 = 0x00;	/* 0db CSU, transmitter off, -36dB EGL */
			reg7a |= ((sp->config.iftxlevel & 0x3) << 3);	/* Linear gain */
		}
		// reg78 &= ~0x01; /* disable transmitter */

		xlb[0x78] = reg78;
		xlb[0x7b] = 0x0a;	/* 100 ohm, MCLK 2.048 MHz */
		xlb[0x7a] = reg7a;

		{
			int byte, c;
			unsigned short mask = 0;

			/* establish which channels are clear channel */
			for (c = 0; c < 24; c++) {
				int slot = xp_t1_chan_map[c];

				byte = c >> 3;
				if (sp->slots[slot]
				    && sp->slots[slot]->sdl.config.iftype == SDL_TYPE_DS0A)
					mask |= 1 << (c % 8);
				if ((c % 8) == 7) {
					xlb[0x08 + byte] = mask;
					mask = 0;
				}
			}
		}
		break;
	}
	}
	// sp->config.ifflags = SDL_IF_UP;
	return (0);
}

STATIC noinline __unlikely int
xp_span_reconfig(struct cd *cd, int span)
{
	struct sp *sp = cd->spans[span];
	volatile unsigned char *xlb = &cd->xlb[span << 8];

	switch (cd->board) {
	case V400PE:
	case E400P:
	case E400PSS7:
	{
		uint8_t ccr1 = 0, tcr1 = 0, reg18 = 0, regac = 0;

		switch (sp->config.ifframing) {
		default:
		case SDL_FRAMING_CCS:
			ccr1 |= 0x08;
			break;
		case SDL_FRAMING_CAS:
			tcr1 |= 0x20;
			break;
		}
		switch (sp->config.ifcoding) {
		default:
		case SDL_CODING_HDB3:
			ccr1 |= 0x44;
			break;
		case SDL_CODING_AMI:
			ccr1 |= 0x00;
			break;
		}
		switch (sp->config.ifgcrc) {
		case SDL_GCRC_CRC4:
			ccr1 |= 0x11;
			break;
		default:
			ccr1 |= 0x00;
			break;
		}
		xlb[0x12] = tcr1;
		xlb[0x14] = ccr1;

		if (sp->config.iftxlevel < 8) {
			/* not monitoring mode */
			regac = 0x00;	/* TEST3 no gain */
			reg18 = 0x00;	/* 75 Ohm, Normal, transmitter on */
			reg18 |= ((sp->config.iftxlevel & 0x7) << 5);	/* LBO */
		} else {
			/* monitoring mode */
			regac = 0x00;	/* TEST3 no gain */
			reg18 = 0x01;	/* 75 Ohm norm, transmitter off */
			switch (sp->config.iftxlevel & 0x3) {
			case 0:
				break;
			case 1:
				regac |= 0x72;	/* TEST3 12dB gain */
				break;
			case 2:
			case 3:
				regac |= 0x70;	/* TEST3 30dB gain */
				break;
			}
		}

		xlb[0xac] = regac;
		xlb[0x18] = reg18;
		break;
	}
	case V401PE:
	{
		u_char reg33, reg35, reg40, reg70, reg78, reg7a;

		switch (sp->config.ifclock) {
		default:
			sp->config.ifclock = SDL_CLOCK_LOOP;
		case SDL_CLOCK_LOOP:
			reg70 = 0x06;	/* Use the signal present at RCLK as the transmit clokc.
					   The TCLK pin is ignored. */
			break;
		case SDL_CLOCK_INT:
			reg70 = 0x00;	/* The TCLK pin is always the source of transmit clock. */
			break;
		case SDL_CLOCK_MASTER:
			reg70 = 0x04;	/* Use the scaled signal present at MCLK as the transmit
					   clock.  The TCLK pin is ignored. */
			break;
		case SDL_CLOCK_EXT:
			reg70 = 0x84;	/* Use the scaled signal present at TSYSCLK as the transmit
					   clock.  The TCLK pin is ignored. */
			break;
		case SDL_CLOCK_SLAVE:
			reg70 = 0x02;	/* Switch to the clock present at RCLK when the signal at
					   the TCLK pin fails to transition after 1 channel time. */
			break;
		}

		/* There are four synchronization modes: 0x00 TCLK only, 0x02 switch to RCLK if
		   TCLK fails, 0x04 external clock, 0x06 loop.  And then 0x80 selects the TSYSCLK
		   pin instead of the MCLK pin when in external clock mode. */
		/* Hmmm. tor3 driver has TCLK only for T1, but RCLK if TCLK fails for E1! */
		xlb[0x70] = reg70;	/* LOTCMC into TCSS0 */

		reg33 = 0x00;
		reg35 = 0x10;	/* TSiS */
		reg40 = 0x00;

		switch (sp->config.ifframing) {
		default:
			sp->config.ifframing = SDL_FRAMING_CCS;
		case SDL_FRAMING_CCS:
			reg40 |= 0x06;
			reg33 |= 0x40;
			break;
		case SDL_FRAMING_CAS:
			break;
		}
		switch (sp->config.ifcoding) {
		default:
			sp->config.ifcoding = SDL_CODING_HDB3;
		case SDL_CODING_HDB3:
			reg33 |= 0x20;
			reg35 |= 0x04;
			break;
		case SDL_CODING_AMI:
			break;
		}
		switch (sp->config.ifgcrc) {
		case SDL_GCRC_CRC4:
			reg33 |= 0x08;
			reg35 |= 0x01;
			break;
		default:
			break;
		}
		/* We could be setting automatic report alarm generation (0x01) (T1) or automatic
		   AIS generation (0x02) (E1). */
		xlb[0x35] = reg35;	/* TSiS, TCRC4 (from 014.4), THDB3 (from O14.6) */
		xlb[0x40] = reg40;	/* RCCS, TCCS */
		xlb[0x33] = reg33 | 0x01;	/* RCR4, RHDB3, RSM, SYNCE, RESYNC */
		xlb[0x33] = reg33 | 0x00;	/* RCR4, RHDB3, RSM, SYNCE */

		if (sp->config.iftxlevel < 8) {
			r