s5x532.h

用于三星S3C2440A和S3C24A0A的VGA或SXGA驱动程序

/*
 * 2004 (C) Samsung Electronics 
 *  SW.LEE <[e-mail]>
 * This file is subject to the terms and conditions of the GNU General Public
 * License 2. See the file COPYING in the main directory of this archive
 * for more details.
 */


#ifndef _SMDK2440_S5X532_H_
#define _SMDK2440_S5X532_H_


#define CHIP_DELAY 0xFF

typedef struct samsung_t{
	unsigned char subaddr;
	unsigned char value;
	unsigned char page; 	
} s5x532_t;

s5x532_t s5x532_reg[] = {
	// page 5
	{0xec,0x05},
	{0x08,0x55,0x5},
	{0x0a,0x75,0x5},
	{0x0c,0x90,0x5},
	{0x0e,0x18,0x5},
	{0x12,0x09,0x5},
	{0x14,0x9d,0x5},
	{0x16,0x90,0x5},
	{0x1a,0x18,0x5},
	{0x1c,0x0c,0x5},
	{0x1e,0x09,0x5},
	{0x20,0x06,0x5},
	{0x22,0x20,0x5},
	{0x2a,0x00,0x5},
	{0x2d,0x04,0x5},
	{0x12,0x24,0x5},
	// page 3
	{0xec,0x03,0x3},
	{0x0c,0x09,0x3},
	{0x6c,0x09,0x3},
	{0x2b,0x10,0x3}, // momo clock inversion
	// page 2
	{0xec,0x02,0x2},
	{0x03,0x09,0x2},
	{0x05,0x08,0x2},
	{0x06,0x01,0x2},
	{0x07,0xf8,0x2},
	{0x15,0x25,0x2},
	{0x30,0x29,0x2},
	{0x36,0x12,0x2},
	{0x38,0x04,0x2},
	{0x1b,0x77,0x2}, // 24MHz : 0x77, 12MHz : 0x22
	{0x1c,0x77,0x2}, // 24MHz : 0x77, 12MHz : 0x22
	// page 1
	{0xec,0x01,0x1},
	{0x00,0x03,0x1}, // 
	{0x0a,0x08,0x1}, // 0x0-QQVGA, 0x06-CIF, 0x02-QCIF, 0x08-VGA, 0x04-QVGA, 0x0a-SXGA
	{0x0c,0x00,0x1}, // Pattern selectio. 0-CIS, 1-Color bar, 2-Ramp, 3-Blue screen
	{0x10,0x27,0x1},
	// 0x21-ITU-R656(CrYCbY), 0x25-ITU-R601(CrYCbY), 0x26-ITU-R601(YCbYCr)
	{0x50,0x21,0x1},		// Hblank
	{0x51,0x00,0x1},		// Hblank
	{0x52,0xA1,0x1},		// Hblank
	{0x53,0x02,0x1},		// Hblank
	{0x54,0x01,0x1},		// Vblank
	{0x55,0x00,0x1},		// Vblank
	{0x56,0xE1,0x1},		// Vblank 		
	{0x57,0x01,0x1},		// Vblank
	{0x58,0x21,0x1},		// Hsync
	{0x59,0x00,0x1},		// Hsync
	{0x5a,0xA1,0x1},		// Hsync
	{0x5b,0x02,0x1},		// Hsync
	{0x5c,0x03,0x1},		// Vref
	{0x5d,0x00,0x1},		// Vref
	{0x5e,0x05,0x1},		// Vref
	{0x5f,0x00,0x1},		// Vref	
	{0x70,0x0E,0x1},
	{0x71,0xD6,0x1},
	{0x72,0x30,0x1},
	{0x73,0xDB,0x1},
	{0x74,0x0E,0x1},
	{0x75,0xD6,0x1},
	{0x76,0x18,0x1},
	{0x77,0xF5,0x1},
	{0x78,0x0E,0x1},
	{0x79,0xD6,0x1},
	{0x7a,0x28,0x1},
	{0x7b,0xE6,0x1},
	{0x50,0x00,0x1},
	{0x5c,0x00,0x1},

	// page 0
	{0xec,0x00,0x0},
	{0x79,0x01,0x0},
	{0x58,0x90,0x0},
	{0x59,0xA0,0x0},
	{0x5a,0x50,0x0},
	{0x5b,0x70,0x0},
	{0x5c,0xD0,0x0},
	{0x5d,0xC0,0x0},
	{0x5e,0x28,0x0},
	{0x5f,0x08,0x0},
	{0x50,0x90,0x0},
	{0x51,0xA0,0x0},
	{0x52,0x50,0x0},
	{0x53,0x70,0x0},
	{0x54,0xD0,0x0},
	{0x55,0xC0,0x0},
	{0x56,0x28,0x0},
	{0x57,0x00,0x0},
	{0x48,0x90,0x0},
	{0x49,0xA0,0x0},
	{0x4a,0x50,0x0},
	{0x4b,0x70,0x0},
	{0x4c,0xD0,0x0},
	{0x4d,0xC0,0x0},
	{0x4e,0x28,0x0},
	{0x4f,0x08,0x0},
	{0x72,0x82,0x0}, // main clock = 24MHz:0xd2, 16M:0x82, 12M:0x54
	{0x75,0x05,0x0} // absolute vertical mirror.  junon

};


#define S5X532_INIT_REGS (sizeof(s5x532_reg)/sizeof(s5x532_reg[0]))
#define S5X532_RISC_REGS 0xEB  
#define S5X532_ISP_REGS 0xFB /* S5C7323X */
#define S5X532_CIS_REGS 0x2F /* S5K437LA03 */


#define PAGE_ADDRESS      0xEC

//#define S5X532_REGS (S5X532_RISC_REGS+S5X532_ISP_REGS+S5X532_CIS_REGS)
#define S5X532_REGS (0x1000)



#endif