dds_vhdl.map.eqn

VHDL 实现DDS的数字移相信号发生器的设计代码.直接解压打开就可以运行..自己写的代码

S2_q_a[4]_PORT_A_data_in = VCC;
S2_q_a[4]_PORT_A_data_in_reg = DFFE(S2_q_a[4]_PORT_A_data_in, S2_q_a[4]_clock_0, , , );
S2_q_a[4]_PORT_B_data_in = T2_ram_rom_data_reg[4];
S2_q_a[4]_PORT_B_data_in_reg = DFFE(S2_q_a[4]_PORT_B_data_in, S2_q_a[4]_clock_1, , , );
S2_q_a[4]_PORT_A_address = BUS(D1_DOUT[22], D1_DOUT[23], D1_DOUT[24], D1_DOUT[25], D1_DOUT[26], D1_DOUT[27], D1_DOUT[28], D1_DOUT[29], D1_DOUT[30], D1_DOUT[31]);
S2_q_a[4]_PORT_A_address_reg = DFFE(S2_q_a[4]_PORT_A_address, S2_q_a[4]_clock_0, , , );
S2_q_a[4]_PORT_B_address = BUS(V2_safe_q[0], V2_safe_q[1], V2_safe_q[2], V2_safe_q[3], V2_safe_q[4], V2_safe_q[5], V2_safe_q[6], V2_safe_q[7], V2_safe_q[8], V2_safe_q[9]);
S2_q_a[4]_PORT_B_address_reg = DFFE(S2_q_a[4]_PORT_B_address, S2_q_a[4]_clock_1, , , );
S2_q_a[4]_PORT_A_write_enable = GND;
S2_q_a[4]_PORT_A_write_enable_reg = DFFE(S2_q_a[4]_PORT_A_write_enable, S2_q_a[4]_clock_0, , , );
S2_q_a[4]_PORT_B_write_enable = T2L62;
S2_q_a[4]_PORT_B_write_enable_reg = DFFE(S2_q_a[4]_PORT_B_write_enable, S2_q_a[4]_clock_1, , , );
S2_q_a[4]_clock_0 = X1__clk0;
S2_q_a[4]_clock_1 = A1L5;
S2_q_a[4]_PORT_A_data_out = MEMORY(S2_q_a[4]_PORT_A_data_in_reg, S2_q_a[4]_PORT_B_data_in_reg, S2_q_a[4]_PORT_A_address_reg, S2_q_a[4]_PORT_B_address_reg, S2_q_a[4]_PORT_A_write_enable_reg, S2_q_a[4]_PORT_B_write_enable_reg, , , S2_q_a[4]_clock_0, S2_q_a[4]_clock_1, , , , );
S2_q_a[4] = S2_q_a[4]_PORT_A_data_out[0];

--S2_q_b[4] is sin_rom:u6|altsyncram:altsyncram_component|altsyncram_m9t:auto_generated|altsyncram_t5b2:altsyncram1|q_b[4]
S2_q_b[4]_PORT_A_data_in = VCC;
S2_q_b[4]_PORT_A_data_in_reg = DFFE(S2_q_b[4]_PORT_A_data_in, S2_q_b[4]_clock_0, , , );
S2_q_b[4]_PORT_B_data_in = T2_ram_rom_data_reg[4];
S2_q_b[4]_PORT_B_data_in_reg = DFFE(S2_q_b[4]_PORT_B_data_in, S2_q_b[4]_clock_1, , , );
S2_q_b[4]_PORT_A_address = BUS(D1_DOUT[22], D1_DOUT[23], D1_DOUT[24], D1_DOUT[25], D1_DOUT[26], D1_DOUT[27], D1_DOUT[28], D1_DOUT[29], D1_DOUT[30], D1_DOUT[31]);
S2_q_b[4]_PORT_A_address_reg = DFFE(S2_q_b[4]_PORT_A_address, S2_q_b[4]_clock_0, , , );
S2_q_b[4]_PORT_B_address = BUS(V2_safe_q[0], V2_safe_q[1], V2_safe_q[2], V2_safe_q[3], V2_safe_q[4], V2_safe_q[5], V2_safe_q[6], V2_safe_q[7], V2_safe_q[8], V2_safe_q[9]);
S2_q_b[4]_PORT_B_address_reg = DFFE(S2_q_b[4]_PORT_B_address, S2_q_b[4]_clock_1, , , );
S2_q_b[4]_PORT_A_write_enable = GND;
S2_q_b[4]_PORT_A_write_enable_reg = DFFE(S2_q_b[4]_PORT_A_write_enable, S2_q_b[4]_clock_0, , , );
S2_q_b[4]_PORT_B_write_enable = T2L62;
S2_q_b[4]_PORT_B_write_enable_reg = DFFE(S2_q_b[4]_PORT_B_write_enable, S2_q_b[4]_clock_1, , , );
S2_q_b[4]_clock_0 = X1__clk0;
S2_q_b[4]_clock_1 = A1L5;
S2_q_b[4]_PORT_B_data_out = MEMORY(S2_q_b[4]_PORT_A_data_in_reg, S2_q_b[4]_PORT_B_data_in_reg, S2_q_b[4]_PORT_A_address_reg, S2_q_b[4]_PORT_B_address_reg, S2_q_b[4]_PORT_A_write_enable_reg, S2_q_b[4]_PORT_B_write_enable_reg, , , S2_q_b[4]_clock_0, S2_q_b[4]_clock_1, , , , );
S2_q_b[4] = S2_q_b[4]_PORT_B_data_out[0];


--S2_q_a[3] is sin_rom:u6|altsyncram:altsyncram_component|altsyncram_m9t:auto_generated|altsyncram_t5b2:altsyncram1|q_a[3]
--RAM Block Operation Mode: True Dual-Port
--Port A Depth: 1024, Port A Width: 1, Port B Depth: 1024, Port B Width: 1
--Port A Logical Depth: 1024, Port A Logical Width: 10, Port B Logical Depth: 1024, Port B Logical Width: 10
--Port A Input: Registered, Port A Output: Un-registered, Port B Input: Registered, Port B Output: Un-registered
S2_q_a[3]_PORT_A_data_in = VCC;
S2_q_a[3]_PORT_A_data_in_reg = DFFE(S2_q_a[3]_PORT_A_data_in, S2_q_a[3]_clock_0, , , );
S2_q_a[3]_PORT_B_data_in = T2_ram_rom_data_reg[3];
S2_q_a[3]_PORT_B_data_in_reg = DFFE(S2_q_a[3]_PORT_B_data_in, S2_q_a[3]_clock_1, , , );
S2_q_a[3]_PORT_A_address = BUS(D1_DOUT[22], D1_DOUT[23], D1_DOUT[24], D1_DOUT[25], D1_DOUT[26], D1_DOUT[27], D1_DOUT[28], D1_DOUT[29], D1_DOUT[30], D1_DOUT[31]);
S2_q_a[3]_PORT_A_address_reg = DFFE(S2_q_a[3]_PORT_A_address, S2_q_a[3]_clock_0, , , );
S2_q_a[3]_PORT_B_address = BUS(V2_safe_q[0], V2_safe_q[1], V2_safe_q[2], V2_safe_q[3], V2_safe_q[4], V2_safe_q[5], V2_safe_q[6], V2_safe_q[7], V2_safe_q[8], V2_safe_q[9]);
S2_q_a[3]_PORT_B_address_reg = DFFE(S2_q_a[3]_PORT_B_address, S2_q_a[3]_clock_1, , , );
S2_q_a[3]_PORT_A_write_enable = GND;
S2_q_a[3]_PORT_A_write_enable_reg = DFFE(S2_q_a[3]_PORT_A_write_enable, S2_q_a[3]_clock_0, , , );
S2_q_a[3]_PORT_B_write_enable = T2L62;
S2_q_a[3]_PORT_B_write_enable_reg = DFFE(S2_q_a[3]_PORT_B_write_enable, S2_q_a[3]_clock_1, , , );
S2_q_a[3]_clock_0 = X1__clk0;
S2_q_a[3]_clock_1 = A1L5;
S2_q_a[3]_PORT_A_data_out = MEMORY(S2_q_a[3]_PORT_A_data_in_reg, S2_q_a[3]_PORT_B_data_in_reg, S2_q_a[3]_PORT_A_address_reg, S2_q_a[3]_PORT_B_address_reg, S2_q_a[3]_PORT_A_write_enable_reg, S2_q_a[3]_PORT_B_write_enable_reg, , , S2_q_a[3]_clock_0, S2_q_a[3]_clock_1, , , , );
S2_q_a[3] = S2_q_a[3]_PORT_A_data_out[0];

--S2_q_b[3] is sin_rom:u6|altsyncram:altsyncram_component|altsyncram_m9t:auto_generated|altsyncram_t5b2:altsyncram1|q_b[3]
S2_q_b[3]_PORT_A_data_in = VCC;
S2_q_b[3]_PORT_A_data_in_reg = DFFE(S2_q_b[3]_PORT_A_data_in, S2_q_b[3]_clock_0, , , );
S2_q_b[3]_PORT_B_data_in = T2_ram_rom_data_reg[3];
S2_q_b[3]_PORT_B_data_in_reg = DFFE(S2_q_b[3]_PORT_B_data_in, S2_q_b[3]_clock_1, , , );
S2_q_b[3]_PORT_A_address = BUS(D1_DOUT[22], D1_DOUT[23], D1_DOUT[24], D1_DOUT[25], D1_DOUT[26], D1_DOUT[27], D1_DOUT[28], D1_DOUT[29], D1_DOUT[30], D1_DOUT[31]);
S2_q_b[3]_PORT_A_address_reg = DFFE(S2_q_b[3]_PORT_A_address, S2_q_b[3]_clock_0, , , );
S2_q_b[3]_PORT_B_address = BUS(V2_safe_q[0], V2_safe_q[1], V2_safe_q[2], V2_safe_q[3], V2_safe_q[4], V2_safe_q[5], V2_safe_q[6], V2_safe_q[7], V2_safe_q[8], V2_safe_q[9]);
S2_q_b[3]_PORT_B_address_reg = DFFE(S2_q_b[3]_PORT_B_address, S2_q_b[3]_clock_1, , , );
S2_q_b[3]_PORT_A_write_enable = GND;
S2_q_b[3]_PORT_A_write_enable_reg = DFFE(S2_q_b[3]_PORT_A_write_enable, S2_q_b[3]_clock_0, , , );
S2_q_b[3]_PORT_B_write_enable = T2L62;
S2_q_b[3]_PORT_B_write_enable_reg = DFFE(S2_q_b[3]_PORT_B_write_enable, S2_q_b[3]_clock_1, , , );
S2_q_b[3]_clock_0 = X1__clk0;
S2_q_b[3]_clock_1 = A1L5;
S2_q_b[3]_PORT_B_data_out = MEMORY(S2_q_b[3]_PORT_A_data_in_reg, S2_q_b[3]_PORT_B_data_in_reg, S2_q_b[3]_PORT_A_address_reg, S2_q_b[3]_PORT_B_address_reg, S2_q_b[3]_PORT_A_write_enable_reg, S2_q_b[3]_PORT_B_write_enable_reg, , , S2_q_b[3]_clock_0, S2_q_b[3]_clock_1, , , , );
S2_q_b[3] = S2_q_b[3]_PORT_B_data_out[0];


--S2_q_a[2] is sin_rom:u6|altsyncram:altsyncram_component|altsyncram_m9t:auto_generated|altsyncram_t5b2:altsyncram1|q_a[2]
--RAM Block Operation Mode: True Dual-Port
--Port A Depth: 1024, Port A Width: 1, Port B Depth: 1024, Port B Width: 1
--Port A Logical Depth: 1024, Port A Logical Width: 10, Port B Logical Depth: 1024, Port B Logical Width: 10
--Port A Input: Registered, Port A Output: Un-registered, Port B Input: Registered, Port B Output: Un-registered
S2_q_a[2]_PORT_A_data_in = VCC;
S2_q_a[2]_PORT_A_data_in_reg = DFFE(S2_q_a[2]_PORT_A_data_in, S2_q_a[2]_clock_0, , , );
S2_q_a[2]_PORT_B_data_in = T2_ram_rom_data_reg[2];
S2_q_a[2]_PORT_B_data_in_reg = DFFE(S2_q_a[2]_PORT_B_data_in, S2_q_a[2]_clock_1, , , );
S2_q_a[2]_PORT_A_address = BUS(D1_DOUT[22], D1_DOUT[23], D1_DOUT[24], D1_DOUT[25], D1_DOUT[26], D1_DOUT[27], D1_DOUT[28], D1_DOUT[29], D1_DOUT[30], D1_DOUT[31]);
S2_q_a[2]_PORT_A_address_reg = DFFE(S2_q_a[2]_PORT_A_address, S2_q_a[2]_clock_0, , , );
S2_q_a[2]_PORT_B_address = BUS(V2_safe_q[0], V2_safe_q[1], V2_safe_q[2], V2_safe_q[3], V2_safe_q[4], V2_safe_q[5], V2_safe_q[6], V2_safe_q[7], V2_safe_q[8], V2_safe_q[9]);
S2_q_a[2]_PORT_B_address_reg = DFFE(S2_q_a[2]_PORT_B_address, S2_q_a[2]_clock_1, , , );
S2_q_a[2]_PORT_A_write_enable = GND;
S2_q_a[2]_PORT_A_write_enable_reg = DFFE(S2_q_a[2]_PORT_A_write_enable, S2_q_a[2]_clock_0, , , );
S2_q_a[2]_PORT_B_write_enable = T2L62;
S2_q_a[2]_PORT_B_write_enable_reg = DFFE(S2_q_a[2]_PORT_B_write_enable, S2_q_a[2]_clock_1, , , );
S2_q_a[2]_clock_0 = X1__clk0;
S2_q_a[2]_clock_1 = A1L5;
S2_q_a[2]_PORT_A_data_out = MEMORY(S2_q_a[2]_PORT_A_data_in_reg, S2_q_a[2]_PORT_B_data_in_reg, S2_q_a[2]_PORT_A_address_reg, S2_q_a[2]_PORT_B_address_reg, S2_q_a[2]_PORT_A_write_enable_reg, S2_q_a[2]_PORT_B_write_enable_reg, , , S2_q_a[2]_clock_0, S2_q_a[2]_clock_1, , , , );
S2_q_a[2] = S2_q_a[2]_PORT_A_data_out[0];

--S2_q_b[2] is sin_rom:u6|altsyncram:altsyncram_component|altsyncram_m9t:auto_generated|altsyncram_t5b2:altsyncram1|q_b[2]
S2_q_b[2]_PORT_A_data_in = VCC;
S2_q_b[2]_PORT_A_data_in_reg = DFFE(S2_q_b[2]_PORT_A_data_in, S2_q_b[2]_clock_0, , , );
S2_q_b[2]_PORT_B_data_in = T2_ram_rom_data_reg[2];
S2_q_b[2]_PORT_B_data_in_reg = DFFE(S2_q_b[2]_PORT_B_data_in, S2_q_b[2]_clock_1, , , );
S2_q_b[2]_PORT_A_address = BUS(D1_DOUT[22], D1_DOUT[23], D1_DOUT[24], D1_DOUT[25], D1_DOUT[26], D1_DOUT[27], D1_DOUT[28], D1_DOUT[29], D1_DOUT[30], D1_DOUT[31]);
S2_q_b[2]_PORT_A_address_reg = DFFE(S2_q_b[2]_PORT_A_address, S2_q_b[2]_clock_0, , , );
S2_q_b[2]_PORT_B_address = BUS(V2_safe_q[0], V2_safe_q[1], V2_safe_q[2], V2_safe_q[3], V2_safe_q[4], V2_safe_q[5], V2_safe_q[6], V2_safe_q[7], V2_safe_q[8], V2_safe_q[9]);
S2_q_b[2]_PORT_B_address_reg = DFFE(S2_q_b[2]_PORT_B_address, S2_q_b[2]_clock_1, , , );
S2_q_b[2]_PORT_A_write_enable = GND;
S2_q_b[2]_PORT_A_write_enable_reg = DFFE(S2_q_b[2]_PORT_A_write_enable, S2_q_b[2]_clock_0, , , );
S2_q_b[2]_PORT_B_write_enable = T2L62;
S2_q_b[2]_PORT_B_write_enable_reg = DFFE(S2_q_b[2]_PORT_B_write_enable, S2_q_b[2]_clock_1, , , );
S2_q_b[2]_clock_0 = X1__clk0;
S2_q_b[2]_clock_1 = A1L5;
S2_q_b[2]_PORT_B_data_out = MEMORY(S2_q_b[2]_PORT_A_data_in_reg, S2_q_b[2]_PORT_B_data_in_reg, S2_q_b[2]_PORT_A_address_reg, S2_q_b[2]_PORT_B_address_reg, S2_q_b[2]_PORT_A_write_enable_reg, S2_q_b[2]_PORT_B_write_enable_reg, , , S2_q_b[2]_clock_0, S2_q_b[2]_clock_1, , , , );
S2_q_b[2] = S2_q_b[2]_PORT_B_data_out[0];


--S2_q_a[1] is sin_rom:u6|altsyncram:altsyncram_component|altsyncram_m9t:auto_generated|altsyncram_t5b2:altsyncram1|q_a[1]
--RAM Block Operation Mode: True Dual-Port
--Port A Depth: 1024, Port A Width: 1, Port B Depth: 1024, Port B Width: 1
--Port A Logical Depth: 1024, Port A Logical Width: 10, Port B Logical Depth: 1024, Port B Logical Width: 10
--Port A Input: Registered, Port A Output: Un-registered, Port B Input: Registered, Port B Output: Un-registered
S2_q_a[1]_PORT_A_data_in = VCC;
S2_q_a[1]_PORT_A_data_in_reg = DFFE(S2_q_a[1]_PORT_A_data_in, S2_q_a[1]_clock_0, , , );
S2_q_a[1]_PORT_B_data_in = T2_ram_rom_data_reg[1];
S2_q_a[1]_PORT_B_data_in_reg = DFFE(S2_q_a[1]_PORT_B_data_in, S2_q_a[1]_clock_1, , , );
S2_q_a[1]_PORT_A_address = BUS(D1_DOUT[22], D1_DOUT[23], D1_DOUT[24], D1_DOUT[25], D1_DOUT[26], D1_DOUT[27], D1_DOUT[28], D1_DOUT[29], D1_DOUT[30], D1_DOUT[31]);
S2_q_a[1]_PORT_A_address_reg = DFFE(S2_q_a[1]_PORT_A_address, S2_q_a[1]_clock_0, , , );
S2_q_a[1]_PORT_B_address = BUS(V2_safe_q[0], V2_safe_q[1], V2_safe_q[2], V2_safe_q[3], V2_safe_q[4], V2_safe_q[5], V2_safe_q[6], V2_safe_q[7], V2_safe_q[8], V2_safe_q[9]);
S2_q_a[1]_PORT_B_address_reg = DFFE(S2_q_a[1]_PORT_B_address, S2_q_a[1]_clock_1, , , );
S2_q_a[1]_PORT_A_write_enable = GND;
S2_q_a[1]_PORT_A_write_enable_reg = DFFE(S2_q_a[1]_PORT_A_write_enable, S2_q_a[1]_clock_0, , , );
S2_q_a[1]_PORT_B_write_enable = T2L62;
S2_q_a[1]_PORT_B_write_enable_reg = DFFE(S2_q_a[1]_PORT_B_write_enable, S2_q_a[1]_clock_1, , , );
S2_q_a[1]_clock_0 = X1__clk0;
S2_q_a[1]_clock_1 = A1L5;
S2_q_a[1]_PORT_A_data_out = MEMORY(S2_q_a[1]_PORT_A_data_in_reg, S2_q_a[1]_PORT_B_data_in_reg, S2_q_a[1]_PORT_A_address_reg, S2_q_a[1]_PORT_B_address_reg, S2_q_a[1]_PORT_A_write_enable_reg, S2_q_a[1]_PORT_B_write_enable_reg, , , S2_q_a[1]_clock_0, S2_q_a[1]_clock_1, , , , );
S2_q_a[1] = S2_q_a[1]_PORT_A_data_out[0];

--S2_q_b[1] is sin_rom:u6|altsyncram:altsyncram_component|altsyncram_m9t:auto_generated|altsyncram_t5b2:altsyncram1|q_b[1]
S2_q_b[1]_PORT_A_data_in = VCC;
S2_q_b[1]_PORT_A_data_in_reg = DFFE(S2_q_b[1]_PORT_A_data_in, S2_q_b[1]_clock_0, , , );
S2_q_b[1]_PORT_B_data_in = T2_ram_rom_data_reg[1];
S2_q_b[1]_PORT_B_data_in_reg = DFFE(S2_q_b[1]_PORT_B_data_in, S2_q_b[1]_clock_1, , , );
S2_q_b[1]_PORT_A_address = BUS(D1_DOUT[22], D1_DOUT[23], D1_DOUT[24], D1_DOUT[25], D1_DOUT[26], D1_DOUT[27], D1_DOUT[28], D1_DOUT[29], D1_DOUT[30], D1_DOUT[31]);
S2_q_b[1]_PORT_A_address_reg = DFFE(S2_q_b[1]_PORT_A_address, S2_q_b[1]_clock_0, , , );
S2_q_b[1]_PORT_B_address = BUS(V2_safe_q[0], V2_safe_q[1], V2_safe_q[2], V2_safe_q[3], V2_safe_q[4], V2_safe_q[5], V2_safe_q[6], V2_safe_q[7], V2_safe_q[8], V2_safe_q[9]);
S2_q_b[1]_PORT_B_address_reg = DFFE(S2_q_b[1]_PORT_B_address, S2_q_b[1]_clock_1, , , );
S2_q_b[1]_PORT_A_write_enable = GND;
S2_q_b[1]_PORT_A_write_enable_reg = DFFE(S2_q_b[1]_PORT_A_write_enable, S2_q_b[1]_clock_0, , , );
S2_q_b[1]_PORT_B_write_enable = T2L62;
S2_q_b[1]_PORT_B_write_enable_reg = DFFE(S2_q_b[1]_PORT_B_write_enable, S2_q_b[1]_clock_1, , , );
S2_q_b[1]_clock_0 = X1__clk0;
S2_q_b[1]_cloc