dds_vhdl.map.eqn

VHDL 实现DDS的数字移相信号发生器的设计代码.直接解压打开就可以运行..自己写的代码

S1_q_b[6]_PORT_B_write_enable = T1L72;
S1_q_b[6]_PORT_B_write_enable_reg = DFFE(S1_q_b[6]_PORT_B_write_enable, S1_q_b[6]_clock_1, , , );
S1_q_b[6]_clock_0 = X1__clk0;
S1_q_b[6]_clock_1 = A1L5;
S1_q_b[6]_PORT_B_data_out = MEMORY(S1_q_b[6]_PORT_A_data_in_reg, S1_q_b[6]_PORT_B_data_in_reg, S1_q_b[6]_PORT_A_address_reg, S1_q_b[6]_PORT_B_address_reg, S1_q_b[6]_PORT_A_write_enable_reg, S1_q_b[6]_PORT_B_write_enable_reg, , , S1_q_b[6]_clock_0, S1_q_b[6]_clock_1, , , , );
S1_q_b[6] = S1_q_b[6]_PORT_B_data_out[0];


--S1_q_a[5] is sin_rom:u3|altsyncram:altsyncram_component|altsyncram_m9t:auto_generated|altsyncram_t5b2:altsyncram1|q_a[5]
--RAM Block Operation Mode: True Dual-Port
--Port A Depth: 1024, Port A Width: 1, Port B Depth: 1024, Port B Width: 1
--Port A Logical Depth: 1024, Port A Logical Width: 10, Port B Logical Depth: 1024, Port B Logical Width: 10
--Port A Input: Registered, Port A Output: Un-registered, Port B Input: Registered, Port B Output: Un-registered
S1_q_a[5]_PORT_A_data_in = VCC;
S1_q_a[5]_PORT_A_data_in_reg = DFFE(S1_q_a[5]_PORT_A_data_in, S1_q_a[5]_clock_0, , , );
S1_q_a[5]_PORT_B_data_in = T1_ram_rom_data_reg[5];
S1_q_a[5]_PORT_B_data_in_reg = DFFE(S1_q_a[5]_PORT_B_data_in, S1_q_a[5]_clock_1, , , );
S1_q_a[5]_PORT_A_address = BUS(G1_DOUT[0], G1_DOUT[1], G1_DOUT[2], G1_DOUT[3], G1_DOUT[4], G1_DOUT[5], G1_DOUT[6], G1_DOUT[7], G1_DOUT[8], G1_DOUT[9]);
S1_q_a[5]_PORT_A_address_reg = DFFE(S1_q_a[5]_PORT_A_address, S1_q_a[5]_clock_0, , , );
S1_q_a[5]_PORT_B_address = BUS(V1_safe_q[0], V1_safe_q[1], V1_safe_q[2], V1_safe_q[3], V1_safe_q[4], V1_safe_q[5], V1_safe_q[6], V1_safe_q[7], V1_safe_q[8], V1_safe_q[9]);
S1_q_a[5]_PORT_B_address_reg = DFFE(S1_q_a[5]_PORT_B_address, S1_q_a[5]_clock_1, , , );
S1_q_a[5]_PORT_A_write_enable = GND;
S1_q_a[5]_PORT_A_write_enable_reg = DFFE(S1_q_a[5]_PORT_A_write_enable, S1_q_a[5]_clock_0, , , );
S1_q_a[5]_PORT_B_write_enable = T1L72;
S1_q_a[5]_PORT_B_write_enable_reg = DFFE(S1_q_a[5]_PORT_B_write_enable, S1_q_a[5]_clock_1, , , );
S1_q_a[5]_clock_0 = X1__clk0;
S1_q_a[5]_clock_1 = A1L5;
S1_q_a[5]_PORT_A_data_out = MEMORY(S1_q_a[5]_PORT_A_data_in_reg, S1_q_a[5]_PORT_B_data_in_reg, S1_q_a[5]_PORT_A_address_reg, S1_q_a[5]_PORT_B_address_reg, S1_q_a[5]_PORT_A_write_enable_reg, S1_q_a[5]_PORT_B_write_enable_reg, , , S1_q_a[5]_clock_0, S1_q_a[5]_clock_1, , , , );
S1_q_a[5] = S1_q_a[5]_PORT_A_data_out[0];

--S1_q_b[5] is sin_rom:u3|altsyncram:altsyncram_component|altsyncram_m9t:auto_generated|altsyncram_t5b2:altsyncram1|q_b[5]
S1_q_b[5]_PORT_A_data_in = VCC;
S1_q_b[5]_PORT_A_data_in_reg = DFFE(S1_q_b[5]_PORT_A_data_in, S1_q_b[5]_clock_0, , , );
S1_q_b[5]_PORT_B_data_in = T1_ram_rom_data_reg[5];
S1_q_b[5]_PORT_B_data_in_reg = DFFE(S1_q_b[5]_PORT_B_data_in, S1_q_b[5]_clock_1, , , );
S1_q_b[5]_PORT_A_address = BUS(G1_DOUT[0], G1_DOUT[1], G1_DOUT[2], G1_DOUT[3], G1_DOUT[4], G1_DOUT[5], G1_DOUT[6], G1_DOUT[7], G1_DOUT[8], G1_DOUT[9]);
S1_q_b[5]_PORT_A_address_reg = DFFE(S1_q_b[5]_PORT_A_address, S1_q_b[5]_clock_0, , , );
S1_q_b[5]_PORT_B_address = BUS(V1_safe_q[0], V1_safe_q[1], V1_safe_q[2], V1_safe_q[3], V1_safe_q[4], V1_safe_q[5], V1_safe_q[6], V1_safe_q[7], V1_safe_q[8], V1_safe_q[9]);
S1_q_b[5]_PORT_B_address_reg = DFFE(S1_q_b[5]_PORT_B_address, S1_q_b[5]_clock_1, , , );
S1_q_b[5]_PORT_A_write_enable = GND;
S1_q_b[5]_PORT_A_write_enable_reg = DFFE(S1_q_b[5]_PORT_A_write_enable, S1_q_b[5]_clock_0, , , );
S1_q_b[5]_PORT_B_write_enable = T1L72;
S1_q_b[5]_PORT_B_write_enable_reg = DFFE(S1_q_b[5]_PORT_B_write_enable, S1_q_b[5]_clock_1, , , );
S1_q_b[5]_clock_0 = X1__clk0;
S1_q_b[5]_clock_1 = A1L5;
S1_q_b[5]_PORT_B_data_out = MEMORY(S1_q_b[5]_PORT_A_data_in_reg, S1_q_b[5]_PORT_B_data_in_reg, S1_q_b[5]_PORT_A_address_reg, S1_q_b[5]_PORT_B_address_reg, S1_q_b[5]_PORT_A_write_enable_reg, S1_q_b[5]_PORT_B_write_enable_reg, , , S1_q_b[5]_clock_0, S1_q_b[5]_clock_1, , , , );
S1_q_b[5] = S1_q_b[5]_PORT_B_data_out[0];


--S1_q_a[4] is sin_rom:u3|altsyncram:altsyncram_component|altsyncram_m9t:auto_generated|altsyncram_t5b2:altsyncram1|q_a[4]
--RAM Block Operation Mode: True Dual-Port
--Port A Depth: 1024, Port A Width: 1, Port B Depth: 1024, Port B Width: 1
--Port A Logical Depth: 1024, Port A Logical Width: 10, Port B Logical Depth: 1024, Port B Logical Width: 10
--Port A Input: Registered, Port A Output: Un-registered, Port B Input: Registered, Port B Output: Un-registered
S1_q_a[4]_PORT_A_data_in = VCC;
S1_q_a[4]_PORT_A_data_in_reg = DFFE(S1_q_a[4]_PORT_A_data_in, S1_q_a[4]_clock_0, , , );
S1_q_a[4]_PORT_B_data_in = T1_ram_rom_data_reg[4];
S1_q_a[4]_PORT_B_data_in_reg = DFFE(S1_q_a[4]_PORT_B_data_in, S1_q_a[4]_clock_1, , , );
S1_q_a[4]_PORT_A_address = BUS(G1_DOUT[0], G1_DOUT[1], G1_DOUT[2], G1_DOUT[3], G1_DOUT[4], G1_DOUT[5], G1_DOUT[6], G1_DOUT[7], G1_DOUT[8], G1_DOUT[9]);
S1_q_a[4]_PORT_A_address_reg = DFFE(S1_q_a[4]_PORT_A_address, S1_q_a[4]_clock_0, , , );
S1_q_a[4]_PORT_B_address = BUS(V1_safe_q[0], V1_safe_q[1], V1_safe_q[2], V1_safe_q[3], V1_safe_q[4], V1_safe_q[5], V1_safe_q[6], V1_safe_q[7], V1_safe_q[8], V1_safe_q[9]);
S1_q_a[4]_PORT_B_address_reg = DFFE(S1_q_a[4]_PORT_B_address, S1_q_a[4]_clock_1, , , );
S1_q_a[4]_PORT_A_write_enable = GND;
S1_q_a[4]_PORT_A_write_enable_reg = DFFE(S1_q_a[4]_PORT_A_write_enable, S1_q_a[4]_clock_0, , , );
S1_q_a[4]_PORT_B_write_enable = T1L72;
S1_q_a[4]_PORT_B_write_enable_reg = DFFE(S1_q_a[4]_PORT_B_write_enable, S1_q_a[4]_clock_1, , , );
S1_q_a[4]_clock_0 = X1__clk0;
S1_q_a[4]_clock_1 = A1L5;
S1_q_a[4]_PORT_A_data_out = MEMORY(S1_q_a[4]_PORT_A_data_in_reg, S1_q_a[4]_PORT_B_data_in_reg, S1_q_a[4]_PORT_A_address_reg, S1_q_a[4]_PORT_B_address_reg, S1_q_a[4]_PORT_A_write_enable_reg, S1_q_a[4]_PORT_B_write_enable_reg, , , S1_q_a[4]_clock_0, S1_q_a[4]_clock_1, , , , );
S1_q_a[4] = S1_q_a[4]_PORT_A_data_out[0];

--S1_q_b[4] is sin_rom:u3|altsyncram:altsyncram_component|altsyncram_m9t:auto_generated|altsyncram_t5b2:altsyncram1|q_b[4]
S1_q_b[4]_PORT_A_data_in = VCC;
S1_q_b[4]_PORT_A_data_in_reg = DFFE(S1_q_b[4]_PORT_A_data_in, S1_q_b[4]_clock_0, , , );
S1_q_b[4]_PORT_B_data_in = T1_ram_rom_data_reg[4];
S1_q_b[4]_PORT_B_data_in_reg = DFFE(S1_q_b[4]_PORT_B_data_in, S1_q_b[4]_clock_1, , , );
S1_q_b[4]_PORT_A_address = BUS(G1_DOUT[0], G1_DOUT[1], G1_DOUT[2], G1_DOUT[3], G1_DOUT[4], G1_DOUT[5], G1_DOUT[6], G1_DOUT[7], G1_DOUT[8], G1_DOUT[9]);
S1_q_b[4]_PORT_A_address_reg = DFFE(S1_q_b[4]_PORT_A_address, S1_q_b[4]_clock_0, , , );
S1_q_b[4]_PORT_B_address = BUS(V1_safe_q[0], V1_safe_q[1], V1_safe_q[2], V1_safe_q[3], V1_safe_q[4], V1_safe_q[5], V1_safe_q[6], V1_safe_q[7], V1_safe_q[8], V1_safe_q[9]);
S1_q_b[4]_PORT_B_address_reg = DFFE(S1_q_b[4]_PORT_B_address, S1_q_b[4]_clock_1, , , );
S1_q_b[4]_PORT_A_write_enable = GND;
S1_q_b[4]_PORT_A_write_enable_reg = DFFE(S1_q_b[4]_PORT_A_write_enable, S1_q_b[4]_clock_0, , , );
S1_q_b[4]_PORT_B_write_enable = T1L72;
S1_q_b[4]_PORT_B_write_enable_reg = DFFE(S1_q_b[4]_PORT_B_write_enable, S1_q_b[4]_clock_1, , , );
S1_q_b[4]_clock_0 = X1__clk0;
S1_q_b[4]_clock_1 = A1L5;
S1_q_b[4]_PORT_B_data_out = MEMORY(S1_q_b[4]_PORT_A_data_in_reg, S1_q_b[4]_PORT_B_data_in_reg, S1_q_b[4]_PORT_A_address_reg, S1_q_b[4]_PORT_B_address_reg, S1_q_b[4]_PORT_A_write_enable_reg, S1_q_b[4]_PORT_B_write_enable_reg, , , S1_q_b[4]_clock_0, S1_q_b[4]_clock_1, , , , );
S1_q_b[4] = S1_q_b[4]_PORT_B_data_out[0];


--S1_q_a[3] is sin_rom:u3|altsyncram:altsyncram_component|altsyncram_m9t:auto_generated|altsyncram_t5b2:altsyncram1|q_a[3]
--RAM Block Operation Mode: True Dual-Port
--Port A Depth: 1024, Port A Width: 1, Port B Depth: 1024, Port B Width: 1
--Port A Logical Depth: 1024, Port A Logical Width: 10, Port B Logical Depth: 1024, Port B Logical Width: 10
--Port A Input: Registered, Port A Output: Un-registered, Port B Input: Registered, Port B Output: Un-registered
S1_q_a[3]_PORT_A_data_in = VCC;
S1_q_a[3]_PORT_A_data_in_reg = DFFE(S1_q_a[3]_PORT_A_data_in, S1_q_a[3]_clock_0, , , );
S1_q_a[3]_PORT_B_data_in = T1_ram_rom_data_reg[3];
S1_q_a[3]_PORT_B_data_in_reg = DFFE(S1_q_a[3]_PORT_B_data_in, S1_q_a[3]_clock_1, , , );
S1_q_a[3]_PORT_A_address = BUS(G1_DOUT[0], G1_DOUT[1], G1_DOUT[2], G1_DOUT[3], G1_DOUT[4], G1_DOUT[5], G1_DOUT[6], G1_DOUT[7], G1_DOUT[8], G1_DOUT[9]);
S1_q_a[3]_PORT_A_address_reg = DFFE(S1_q_a[3]_PORT_A_address, S1_q_a[3]_clock_0, , , );
S1_q_a[3]_PORT_B_address = BUS(V1_safe_q[0], V1_safe_q[1], V1_safe_q[2], V1_safe_q[3], V1_safe_q[4], V1_safe_q[5], V1_safe_q[6], V1_safe_q[7], V1_safe_q[8], V1_safe_q[9]);
S1_q_a[3]_PORT_B_address_reg = DFFE(S1_q_a[3]_PORT_B_address, S1_q_a[3]_clock_1, , , );
S1_q_a[3]_PORT_A_write_enable = GND;
S1_q_a[3]_PORT_A_write_enable_reg = DFFE(S1_q_a[3]_PORT_A_write_enable, S1_q_a[3]_clock_0, , , );
S1_q_a[3]_PORT_B_write_enable = T1L72;
S1_q_a[3]_PORT_B_write_enable_reg = DFFE(S1_q_a[3]_PORT_B_write_enable, S1_q_a[3]_clock_1, , , );
S1_q_a[3]_clock_0 = X1__clk0;
S1_q_a[3]_clock_1 = A1L5;
S1_q_a[3]_PORT_A_data_out = MEMORY(S1_q_a[3]_PORT_A_data_in_reg, S1_q_a[3]_PORT_B_data_in_reg, S1_q_a[3]_PORT_A_address_reg, S1_q_a[3]_PORT_B_address_reg, S1_q_a[3]_PORT_A_write_enable_reg, S1_q_a[3]_PORT_B_write_enable_reg, , , S1_q_a[3]_clock_0, S1_q_a[3]_clock_1, , , , );
S1_q_a[3] = S1_q_a[3]_PORT_A_data_out[0];

--S1_q_b[3] is sin_rom:u3|altsyncram:altsyncram_component|altsyncram_m9t:auto_generated|altsyncram_t5b2:altsyncram1|q_b[3]
S1_q_b[3]_PORT_A_data_in = VCC;
S1_q_b[3]_PORT_A_data_in_reg = DFFE(S1_q_b[3]_PORT_A_data_in, S1_q_b[3]_clock_0, , , );
S1_q_b[3]_PORT_B_data_in = T1_ram_rom_data_reg[3];
S1_q_b[3]_PORT_B_data_in_reg = DFFE(S1_q_b[3]_PORT_B_data_in, S1_q_b[3]_clock_1, , , );
S1_q_b[3]_PORT_A_address = BUS(G1_DOUT[0], G1_DOUT[1], G1_DOUT[2], G1_DOUT[3], G1_DOUT[4], G1_DOUT[5], G1_DOUT[6], G1_DOUT[7], G1_DOUT[8], G1_DOUT[9]);
S1_q_b[3]_PORT_A_address_reg = DFFE(S1_q_b[3]_PORT_A_address, S1_q_b[3]_clock_0, , , );
S1_q_b[3]_PORT_B_address = BUS(V1_safe_q[0], V1_safe_q[1], V1_safe_q[2], V1_safe_q[3], V1_safe_q[4], V1_safe_q[5], V1_safe_q[6], V1_safe_q[7], V1_safe_q[8], V1_safe_q[9]);
S1_q_b[3]_PORT_B_address_reg = DFFE(S1_q_b[3]_PORT_B_address, S1_q_b[3]_clock_1, , , );
S1_q_b[3]_PORT_A_write_enable = GND;
S1_q_b[3]_PORT_A_write_enable_reg = DFFE(S1_q_b[3]_PORT_A_write_enable, S1_q_b[3]_clock_0, , , );
S1_q_b[3]_PORT_B_write_enable = T1L72;
S1_q_b[3]_PORT_B_write_enable_reg = DFFE(S1_q_b[3]_PORT_B_write_enable, S1_q_b[3]_clock_1, , , );
S1_q_b[3]_clock_0 = X1__clk0;
S1_q_b[3]_clock_1 = A1L5;
S1_q_b[3]_PORT_B_data_out = MEMORY(S1_q_b[3]_PORT_A_data_in_reg, S1_q_b[3]_PORT_B_data_in_reg, S1_q_b[3]_PORT_A_address_reg, S1_q_b[3]_PORT_B_address_reg, S1_q_b[3]_PORT_A_write_enable_reg, S1_q_b[3]_PORT_B_write_enable_reg, , , S1_q_b[3]_clock_0, S1_q_b[3]_clock_1, , , , );
S1_q_b[3] = S1_q_b[3]_PORT_B_data_out[0];


--S1_q_a[2] is sin_rom:u3|altsyncram:altsyncram_component|altsyncram_m9t:auto_generated|altsyncram_t5b2:altsyncram1|q_a[2]
--RAM Block Operation Mode: True Dual-Port
--Port A Depth: 1024, Port A Width: 1, Port B Depth: 1024, Port B Width: 1
--Port A Logical Depth: 1024, Port A Logical Width: 10, Port B Logical Depth: 1024, Port B Logical Width: 10
--Port A Input: Registered, Port A Output: Un-registered, Port B Input: Registered, Port B Output: Un-registered
S1_q_a[2]_PORT_A_data_in = VCC;
S1_q_a[2]_PORT_A_data_in_reg = DFFE(S1_q_a[2]_PORT_A_data_in, S1_q_a[2]_clock_0, , , );
S1_q_a[2]_PORT_B_data_in = T1_ram_rom_data_reg[2];
S1_q_a[2]_PORT_B_data_in_reg = DFFE(S1_q_a[2]_PORT_B_data_in, S1_q_a[2]_clock_1, , , );
S1_q_a[2]_PORT_A_address = BUS(G1_DOUT[0], G1_DOUT[1], G1_DOUT[2], G1_DOUT[3], G1_DOUT[4], G1_DOUT[5], G1_DOUT[6], G1_DOUT[7], G1_DOUT[8], G1_DOUT[9]);
S1_q_a[2]_PORT_A_address_reg = DFFE(S1_q_a[2]_PORT_A_address, S1_q_a[2]_clock_0, , , );
S1_q_a[2]_PORT_B_address = BUS(V1_safe_q[0], V1_safe_q[1], V1_safe_q[2], V1_safe_q[3], V1_safe_q[4], V1_safe_q[5], V1_safe_q[6], V1_safe_q[7], V1_safe_q[8], V1_safe_q[9]);
S1_q_a[2]_PORT_B_address_reg = DFFE(S1_q_a[2]_PORT_B_address, S1_q_a[2]_clock_1, , , );
S1_q_a[2]_PORT_A_write_enable = GND;
S1_q_a[2]_PORT_A_write_enable_reg = DFFE(S1_q_a[2]_PORT_A_write_enable, S1_q_a[2]_clock_0, , , );
S1_q_a[2]_PORT_B_write_enable = T1L72;
S1_q_a[2]_PORT_B_write_enable_reg = DFFE(S1_q_a[2]_PORT_B_write_enable, S1_q_a[2]_clock_1, , , );
S1_q_a[2]_clock_0 = X1__clk0;
S1_q_a[2]_clock_1 = A1L5;
S1_q_a[2]_PORT_A_data_out = MEMORY(S1_q_a[2]_PORT_A_data_in_reg, S1_q_a[2]_PORT_B_data_in_reg, S1_q_a[2]_PORT_A_address_reg, S1_q_a[2]_PORT_B_address_reg, S1_q_a[2]_PORT_A_write_enable_reg, S1_q_a[2]_PORT_B_write_enable_reg, , , S1_q_a[2]_clock_0, S1_q_a[2]_clock_1, , , , );
S1_q_a[2] = S1_q_a[2]_PORT_A_data_out[0];

--S1_q_b[2] is sin_rom:u3|altsyncram:altsyncram_component|altsyncram_m9t:auto_generated|altsyncram_t5b2:altsyncram1|q_b[2]
S1_q_b[2]_PORT_A_data_in = VCC;
S1_q_b[2]_PORT_A_data_in_reg = DFFE(S1_q_b[2]_PORT_A_data_in, S1_q_b[2]_clock_0, , , );