dds_vhdl.qsf

VHDL 实现DDS的数字移相信号发生器的设计代码.直接解压打开就可以运行..自己写的代码

# Copyright (C) 1991-2004 Altera Corporation
# Any  megafunction  design,  and related netlist (encrypted  or  decrypted),
# support information,  device programming or simulation file,  and any other
# associated  documentation or information  provided by  Altera  or a partner
# under  Altera's   Megafunction   Partnership   Program  may  be  used  only
# to program  PLD  devices (but not masked  PLD  devices) from  Altera.   Any
# other  use  of such  megafunction  design,  netlist,  support  information,
# device programming or simulation file,  or any other  related documentation
# or information  is prohibited  for  any  other purpose,  including, but not
# limited to  modification,  reverse engineering,  de-compiling, or use  with
# any other  silicon devices,  unless such use is  explicitly  licensed under
# a separate agreement with  Altera  or a megafunction partner.  Title to the
# intellectual property,  including patents,  copyrights,  trademarks,  trade
# secrets,  or maskworks,  embodied in any such megafunction design, netlist,
# support  information,  device programming or simulation file,  or any other
# related documentation or information provided by  Altera  or a megafunction
# partner, remains with Altera, the megafunction partner, or their respective
# licensors. No other licenses, including any licenses needed under any third
# party's intellectual property, are provided herein.


# The default values for assignments are stored in the file
#		dds_vhdl_assignment_defaults.qdf
# If this file doesn't exist, and for assignments not listed, see file
#		assignment_defaults.qdf

# Altera recommends that you do not modify this file. This
# file is updated automatically by the Quartus II software
# and any changes you make may be lost or overwritten.


# Project-Wide Assignments
# ========================
set_global_assignment -name ORIGINAL_QUARTUS_VERSION 4.0
set_global_assignment -name PROJECT_CREATION_TIME_DATE "11:24:38  JULY 10, 2004"
set_global_assignment -name LAST_QUARTUS_VERSION 6.0
set_global_assignment -name VHDL_FILE adder32b.vhd
set_global_assignment -name VHDL_FILE dds_vhdl.vhd
set_global_assignment -name VHDL_FILE reg32b.vhd
set_global_assignment -name VHDL_FILE sin_rom.vhd
set_global_assignment -name VHDL_FILE adder10b.vhd
set_global_assignment -name VHDL_FILE reg10b.vhd
set_global_assignment -name SIGNALTAP_FILE stp1.stp

# Pin & Location Assignments
# ==========================
set_location_assignment PIN_166 -to FOUT\[0\]
set_location_assignment PIN_165 -to FOUT\[1\]
set_location_assignment PIN_164 -to FOUT\[2\]
set_location_assignment PIN_163 -to FOUT\[3\]
set_location_assignment PIN_162 -to FOUT\[4\]
set_location_assignment PIN_161 -to FOUT\[5\]
set_location_assignment PIN_160 -to FOUT\[6\]
set_location_assignment PIN_159 -to FOUT\[7\]
set_location_assignment PIN_158 -to FOUT\[8\]
set_location_assignment PIN_141 -to FOUT\[9\]
set_location_assignment PIN_233 -to FWORD\[0\]
set_location_assignment PIN_234 -to FWORD\[1\]
set_location_assignment PIN_235 -to FWORD\[2\]
set_location_assignment PIN_236 -to FWORD\[3\]
set_location_assignment PIN_237 -to FWORD\[4\]
set_location_assignment PIN_238 -to FWORD\[5\]
set_location_assignment PIN_239 -to FWORD\[6\]
set_location_assignment PIN_240 -to FWORD\[7\]
set_location_assignment PIN_1 -to PWORD\[0\]
set_location_assignment PIN_2 -to PWORD\[1\]
set_location_assignment PIN_3 -to PWORD\[2\]
set_location_assignment PIN_4 -to PWORD\[3\]
set_location_assignment PIN_6 -to PWORD\[4\]
set_location_assignment PIN_7 -to PWORD\[5\]
set_location_assignment PIN_8 -to PWORD\[6\]
set_location_assignment PIN_12 -to PWORD\[7\]
set_location_assignment PIN_140 -to POUT\[0\]
set_location_assignment PIN_139 -to POUT\[1\]
set_location_assignment PIN_138 -to POUT\[2\]
set_location_assignment PIN_137 -to POUT\[3\]
set_location_assignment PIN_136 -to POUT\[4\]
set_location_assignment PIN_135 -to POUT\[5\]
set_location_assignment PIN_134 -to POUT\[6\]
set_location_assignment PIN_133 -to POUT\[7\]
set_location_assignment PIN_132 -to POUT\[8\]
set_location_assignment PIN_128 -to POUT\[9\]
set_location_assignment PIN_28 -to CLKK
set_location_assignment PIN_167 -to CLK_DA

# Analysis & Synthesis Assignments
# ================================
set_global_assignment -name DEVICE_FILTER_PACKAGE PQFP
set_global_assignment -name DEVICE_FILTER_PIN_COUNT 240
set_global_assignment -name DEVICE_FILTER_SPEED_GRADE 8
set_global_assignment -name FAMILY Cyclone
set_global_assignment -name CYCLONE_OPTIMIZATION_TECHNIQUE AREA
set_global_assignment -name TOP_LEVEL_ENTITY DDS_VHDL
set_global_assignment -name AUTO_ENABLE_SMART_COMPILE on

# Fitter Assignments
# ==================
set_global_assignment -name DEVICE EP1C12Q240C8
set_global_assignment -name RESERVE_ASDO_AFTER_CONFIGURATION "AS OUTPUT DRIVING AN UNSPECIFIED SIGNAL"
set_global_assignment -name FITTER_EFFORT "AUTO FIT"

# Assembler Assignments
# =====================
set_global_assignment -name CYCLONE_CONFIGURATION_DEVICE EPCS1

# SignalTap II Assignments
# ========================
set_global_assignment -name ENABLE_SIGNALTAP off
set_global_assignment -name USE_SIGNALTAP_FILE stp1.stp

# LogicLock Region Assignments
# ============================
set_global_assignment -name LOGICLOCK_INCREMENTAL_COMPILE_ASSIGNMENT OFF