dds_vhdl.tan.rpt

来自「VHDL 实现DDS的数字移相信号发生器的设计代码.直接解压打开就可以运行..自」· RPT 代码 · 共 207 行 · 第 1/5 页

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+----------------------------------------------------------------------------------------+
; Timing Analyzer Settings                                                               ;
+-------------------------------------------------------+--------------------+------+----+
; Option                                                ; Setting            ; From ; To ;
+-------------------------------------------------------+--------------------+------+----+
; Device name                                           ; EP1C12Q240C8       ;      ;    ;
; Timing Models                                         ; Production         ;      ;    ;
; Number of source nodes to report per destination node ; 10                 ;      ;    ;
; Number of destination nodes to report                 ; 10                 ;      ;    ;
; Number of paths to report                             ; 200                ;      ;    ;
; Run Minimum Analysis                                  ; On                 ;      ;    ;
; Use Minimum Timing Models                             ; Off                ;      ;    ;
; Report IO Paths Separately                            ; Off                ;      ;    ;
; Clock Analysis Only                                   ; Off                ;      ;    ;
; Default hold multicycle                               ; Same as Multicycle ;      ;    ;
; Cut paths between unrelated clock domains             ; On                 ;      ;    ;
; Cut off read during write signal paths                ; On                 ;      ;    ;
; Cut off clear and preset signal paths                 ; On                 ;      ;    ;
; Cut off feedback from I/O pins                        ; On                 ;      ;    ;
; Ignore Clock Settings                                 ; Off                ;      ;    ;
; Analyze latches as synchronous elements               ; Off                ;      ;    ;
+-------------------------------------------------------+--------------------+------+----+


+----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Timing Analyzer Summary                                                                                                                                                                                                                                                                                                                                                                                                                                                                                              ;
+-------------------------------------------------------+----------+----------------------------------+----------------------------------+--------------------------------------------------------------------------------------------------------------------------------------+-------------------------------------------------------------------------------------------------------------------------------------+----------------------------------------+----------------------------------------+--------------+
; Type                                                  ; Slack    ; Required Time                    ; Actual Time                      ; From                                                                                                                                 ; To                                                                                                                                  ; From Clock                             ; To Clock                               ; Failed Paths ;
+-------------------------------------------------------+----------+----------------------------------+----------------------------------+--------------------------------------------------------------------------------------------------------------------------------------+-------------------------------------------------------------------------------------------------------------------------------------+----------------------------------------+----------------------------------------+--------------+
; Worst-case tsu                                        ; N/A      ; None                             ; 11.347 ns                        ; FWORD[6]                                                                                                                             ; REG32B:u2|DOUT[31]                                                                                                                  ;                                        ; CLKK                                   ; 0            ;
; Worst-case tco                                        ; N/A      ; None                             ; 12.568 ns                        ; sin_rom:u3|altsyncram:altsyncram_component|altsyncram_m9t:auto_generated|altsyncram_t5b2:altsyncram1|ram_block3a9~porta_address_reg9 ; FOUT[0]                                                                                                                             ; CLKK                                   ;                                        ; 0            ;
; Worst-case tpd                                        ; N/A      ; None                             ; 2.124 ns                         ; altera_internal_jtag~TDO                                                                                                             ; altera_reserved_tdo                                                                                                                 ;                                        ;                                        ; 0            ;
; Worst-case th                                         ; N/A      ; None                             ; 3.507 ns                         ; altera_internal_jtag                                                                                                                 ; sld_hub:sld_hub_inst|sld_dffex:IRSR|Q[6]                                                                                            ;                                        ; altera_internal_jtag~TCKUTAP           ; 0            ;
; Worst-case Minimum tco                                ; N/A      ; None                             ; 2.717 ns                         ; PLL20:u7|altpll:altpll_component|_clk0                                                                                               ; CLK_DA                                                                                                                              ; CLKK                                   ;                                        ; 0            ;
; Worst-case Minimum tpd                                ; N/A      ; None                             ; 2.124 ns                         ; altera_internal_jtag~TDO                                                                                                             ; altera_reserved_tdo                                                                                                                 ;                                        ;                                        ; 0            ;