📄 hwdefs.h
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#define SMC_BASE (VIRTUAL_SYSTEM_ASIC_REGS_BASE + 0x00080000)
#define SMC_SMCBCR0 (volatile ULONG *)(SMC_BASE + 0x0000)
#define SMC_SMCBCR1 (volatile ULONG *)(SMC_BASE + 0x0004)
#define SMC_SMCBCR2 (volatile ULONG *)(SMC_BASE + 0x0008)
#define SMC_SMCBCR3 (volatile ULONG *)(SMC_BASE + 0x000C)
#define SMC_RAZ0 (volatile ULONG *)(SMC_BASE + 0x0010)
#define SMC_RAZ1 (volatile ULONG *)(SMC_BASE + 0x0014)
#define SMC_SMCBCR6 (volatile ULONG *)(SMC_BASE + 0x0018)
#define SMC_SMCBCR7 (volatile ULONG *)(SMC_BASE + 0x001C)
#define SMC_PCCONFIG_ATT1 (volatile ULONG *)(SMC_BASE + 0x0020)
#define SMC_PCCONFIG_MEM1 (volatile ULONG *)(SMC_BASE + 0x0024)
#define SMC_PCCONFIG_IO1 (volatile ULONG *)(SMC_BASE + 0x0028)
#define SMC_RAZ2 (volatile ULONG *)(SMC_BASE + 0x002C)
#define SMC_PCCONFIG_ATT2 (volatile ULONG *)(SMC_BASE + 0x0030)
#define SMC_PCCONFIG_MEM2 (volatile ULONG *)(SMC_BASE + 0x0034)
#define SMC_PCCONFIG_IO2 (volatile ULONG *)(SMC_BASE + 0x0038)
#define SMC_RAZ3 (volatile ULONG *)(SMC_BASE + 0x003C)
#define SMC_PCCONT (volatile ULONG *)(SMC_BASE + 0x0040)
//
// Bit Fields for the SMCBCR register definition file.
//
#define SMCBCR_IDCY_MASK 0x0000000F
#define SMCBCR_IDCY_SHIFT 0
#define SMCBCR_WST1_MASK 0x000003E0
#define SMCBCR_WST1_SHIFT 5
#define SMCBCR_RBLE 0x00000400
#define SMCBCR_WST2_MASK 0x0000F800
#define SMCBCR_WST2_SHIFT 11
#define SMCBCR_WPERR 0x02000000
#define SMCBCR_WP 0x04000000
#define SMCBCR_PME 0x08000000
#define SMCBCR_MASK 0x30000000
#define SMCBCR_MW_8BIT 0x00000000
#define SMCBCR_MW_16BIT 0x10000000
#define SMCBCR_MW_32BIT 0x20000000
#define SMCBCR_EBIBRKDIS 0x40000000
//
// PCMCIA configuration registers.
//
#define PCCONFIG_ADDRESSTIME_MASK 0x000000FF
#define PCCONFIG_ADDRESSTIME_SHIFT 0
#define PCCONFIG_HOLDTIME_MASK 0x00000F00
#define PCCONFIG_HOLDTIME_SHIFT 8
#define PCCONFIG_ACCESSTIME_MASK 0x00FF0000
#define PCCONFIG_ACCESSTIME_SHIFT 16
#define PCCONFIG_MW_8BIT 0x00000000
#define PCCONFIG_MW_16BIT 0x80000000
#define PCCONT_PC1EN 0x00000001
#define PCCONT_PC2EN 0x00000002
#define PCCONT_PC1RST 0x00000004
#define PCCONT_PC2RST 0x00000008
#define PCCONT_WEN1 0x00000010
#define PCCONT_WEN2 0x00000020
#define PCCONT_PREG 0x00000040
//
// IDE base - supports only PIO mode IDE access
//
#define IDE_BASE (VIRTUAL_SYSTEM_ASIC_REGS_BASE + 0x000A0000)
#define IDE_CTRL ((volatile ULONG *) (IDE_BASE + 0x0000))
#define IDE_CFG ((volatile ULONG *) (IDE_BASE + 0x0004))
#define IDE_MDMAOP ((volatile ULONG *) (IDE_BASE + 0x0008))
#define IDE_UDMAOP ((volatile ULONG *) (IDE_BASE + 0x000C))
#define IDE_DATAOUT ((volatile ULONG *) (IDE_BASE + 0x0010))
#define IDE_DATAIN ((volatile ULONG *) (IDE_BASE + 0x0014))
#define IDE_MDMADATAOUT ((volatile ULONG *) (IDE_BASE + 0x0018))
#define IDE_MDMADATAIN ((volatile ULONG *) (IDE_BASE + 0x001C))
#define IDE_UDMADATAOUT ((volatile ULONG *) (IDE_BASE + 0x0020))
#define IDE_UDMADATAIN ((volatile ULONG *) (IDE_BASE + 0x0024))
#define IDE_UDMASTATUS ((volatile ULONG *) (IDE_BASE + 0x0028))
#define IDE_UDMADEBUG ((volatile ULONG *) (IDE_BASE + 0x002C))
#define IDE_UDMAWFST ((volatile ULONG *) (IDE_BASE + 0x0030))
#define IDE_UDMARFST ((volatile ULONG *) (IDE_BASE + 0x0034))
#define IDE_CTRL_CS0 0x0001
#define IDE_CTRL_CS1 0x0002
#define IDE_CTRL_DA 0x001C
#define IDE_CTRL_DA_SHIFT 0x0002
#define IDE_CTRL_DA0 0x0004
#define IDE_CTRL_DA1 0x0008
#define IDE_CTRL_DA2 0x0010
#define IDE_CTRL_DIOR 0x0020
#define IDE_CTRL_DIOW 0x0040
#define IDE_CTRL_DASP 0x0080 //read only
#define IDE_CTRL_DMARQ 0x0100 //read only
#define IDE_CTRL_INTRQ 0x0200 //read only
#define IDE_CTRL_IORDY 0x0400 //read only
//
// Definitions to access the individial registers.
//
#define CSDA_DATA_REG (( 0 <<IDE_CTRL_DA_SHIFT) | IDE_CTRL_CS1)
#define CSDA_ERROR_REG (( 1 <<IDE_CTRL_DA_SHIFT) | IDE_CTRL_CS1)
#define CSDA_FEATURE_REG (( 1 <<IDE_CTRL_DA_SHIFT) | IDE_CTRL_CS1)
#define CSDA_REASON_REG (( 2 <<IDE_CTRL_DA_SHIFT) | IDE_CTRL_CS1)
#define CSDA_SECTCNT_REG (( 2 <<IDE_CTRL_DA_SHIFT) | IDE_CTRL_CS1)
#define CSDA_SECTNUM_REG (( 3 <<IDE_CTRL_DA_SHIFT) | IDE_CTRL_CS1)
#define CSDA_CYLL_REG (( 4 <<IDE_CTRL_DA_SHIFT) | IDE_CTRL_CS1)
#define CSDA_CYLH_REG (( 5 <<IDE_CTRL_DA_SHIFT) | IDE_CTRL_CS1)
#define CSDA_DRVHD_REG (( 6 <<IDE_CTRL_DA_SHIFT) | IDE_CTRL_CS1)
#define CSDA_CMD_REG (( 7 <<IDE_CTRL_DA_SHIFT) | IDE_CTRL_CS1)
#define CSDA_STAT_REG (( 7 <<IDE_CTRL_DA_SHIFT) | IDE_CTRL_CS1)
#define CSDA_ALT_CTRL_REG (( 6 <<IDE_CTRL_DA_SHIFT) | IDE_CTRL_CS0)
#define CSDA_ALT_STAT_REG (( 6 <<IDE_CTRL_DA_SHIFT) | IDE_CTRL_CS0)
#define IDE_CFG_IDEEN 0x00000001
#define IDE_CFG_PIOEN 0x00000002
#define IDE_CFG_MDMAEN 0x00000004
#define IDE_CFG_UDMAEN 0x00000008
#define IDE_CFG_MODE_MASK 0x000000F0
#define IDE_CFG_MODE_SHIFT 4
#define IDE_CFG_PIO4 0x00000040
#define IDE_CFG_WST_MASK 0x00000300
#define IDE_CFG_WST_SHIFT 8
#define DMAOP_MEN 0x00000001
#define DMAOP_RWOP 0x00000002
#define IDE_MDMAOP_MEN DMAOP_MEN
#define IDE_MDMAOP_RWOP DMAOP_RWOP
#define IDE_UDMAOP_MEN DMAOP_MEN
#define IDE_UDMAOP_RWOP DMAOP_RWOP
#define UDMASTATUS_CS0 0x00000001
#define UDMASTATUS_CS1 0x00000002
#define UDMASTATUS_DA_MASK 0x0000001C
#define UDMASTATUS_HSHD 0x00000020
#define UDMASTATUS_STOP 0x00000040
#define UDMASTATUS_DM 0x00000080
#define UDMASTATUS_DDOE 0x00000100
#define UDMASTATUS_DMARQ 0x00000200
#define UDMASTATUS_DSDD 0x00000400
#define UDMASTATUS_DMAIDE 0x00010000
#define UDMASTATUS_INTIDE 0x00020000
#define UDMASTATUS_SBUSY 0x00040000
#define UDMASTATUS_NDO 0x01000000
#define UDMASTATUS_NDI 0x02000000
#define UDMASTATUS_N4X 0x04000000
#define UDMADEBUG_RWOE 0x00000001
#define UDMADEBUG_RWPTR 0x00000002
#define UDMADEBUG_RWDR 0x00000004
#define UDMADEBUG_RROE 0x00000008
#define UDMADEBUG_RRPTR 0x00000010
#define UDMADEBUG_RRDR 0x00000020
//
// Vectored Interrupt Controller
//
#define VIC1_BASE (VIRTUAL_SYSTEM_ASIC_REGS_BASE + 0x000B0000)
#define VIC2_BASE (VIRTUAL_SYSTEM_ASIC_REGS_BASE + 0x000C0000)
#define VIC1_IRQSTATUS (volatile ULONG *)(VIC1_BASE + 0x0000)
#define VIC1_FIQSTATUS (volatile ULONG *)(VIC1_BASE + 0x0004)
#define VIC1_RAWINTR (volatile ULONG *)(VIC1_BASE + 0x0008)
#define VIC1_INTSELECT (volatile ULONG *)(VIC1_BASE + 0x000C)
#define VIC1_INTENABLE (volatile ULONG *)(VIC1_BASE + 0x0010)
#define VIC1_INTCLEAR (volatile ULONG *)(VIC1_BASE + 0x0014)
#define VIC1_SOFTINT (volatile ULONG *)(VIC1_BASE + 0x0018)
#define VIC1_SOFTINTCLEAR (volatile ULONG *)(VIC1_BASE + 0x001C)
#define VIC1_PROTECTION (volatile ULONG *)(VIC1_BASE + 0x0020)
#define VIC1_VECTCURADDR (volatile ULONG *)(VIC1_BASE + 0x0030)
#define VIC1_VECTDEFAULT (volatile ULONG *)(VIC1_BASE + 0x0034)
#define VIC1_VECTADDR0 (volatile ULONG *)(VIC1_BASE + 0x0100)
#define VIC1_VECTADDR1 (volatile ULONG *)(VIC1_BASE + 0x0104)
#define VIC1_VECTADDR2 (volatile ULONG *)(VIC1_BASE + 0x0108)
#define VIC1_VECTADDR3 (volatile ULONG *)(VIC1_BASE + 0x010C)
#define VIC1_VECTADDR4 (volatile ULONG *)(VIC1_BASE + 0x0110)
#define VIC1_VECTADDR5 (volatile ULONG *)(VIC1_BASE + 0x0114)
#define VIC1_VECTADDR6 (volatile ULONG *)(VIC1_BASE + 0x0118)
#define VIC1_VECTADDR7 (volatile ULONG *)(VIC1_BASE + 0x011C)
#define VIC1_VECTADDR8 (volatile ULONG *)(VIC1_BASE + 0x0120)
#define VIC1_VECTADDR9 (volatile ULONG *)(VIC1_BASE + 0x0124)
#define VIC1_VECTADDR10 (volatile ULONG *)(VIC1_BASE + 0x0128)
#define VIC1_VECTADDR11 (volatile ULONG *)(VIC1_BASE + 0x012C)
#define VIC1_VECTADDR12 (volatile ULONG *)(VIC1_BASE + 0x0130)
#define VIC1_VECTADDR13 (volatile ULONG *)(VIC1_BASE + 0x0134)
#define VIC1_VECTADDR14 (volatile ULONG *)(VIC1_BASE + 0x0138)
#define VIC1_VECTADDR15 (volatile ULONG *)(VIC1_BASE + 0x013C)
#define VIC1_VECTCNTL0 (volatile ULONG *)(VIC1_BASE + 0x0200)
#define VIC1_VECTCNTL1 (volatile ULONG *)(VIC1_BASE + 0x0204)
#define VIC1_VECTCNTL2 (volatile ULONG *)(VIC1_BASE + 0x0208)
#define VIC1_VECTCNTL3 (volatile ULONG *)(VIC1_BASE + 0x020C)
#define VIC1_VECTCNTL4 (volatile ULONG *)(VIC1_BASE + 0x0210)
#define VIC1_VECTCNTL5 (volatile ULONG *)(VIC1_BASE + 0x0214)
#define VIC1_VECTCNTL6 (volatile ULONG *)(VIC1_BASE + 0x0218)
#define VIC1_VECTCNTL7 (volatile ULONG *)(VIC1_BASE + 0x021C)
#define VIC1_VECTCNTL8 (volatile ULONG *)(VIC1_BASE + 0x0220)
#define VIC1_VECTCNTL9 (volatile ULONG *)(VIC1_BASE + 0x0224)
#define VIC1_VECTCNTL10 (volatile ULONG *)(VIC1_BASE + 0x0228)
#define VIC1_VECTCNTL11 (volatile ULONG *)(VIC1_BASE + 0x022C)
#define VIC1_VECTCNTL12 (volatile ULONG *)(VIC1_BASE + 0x0230)
#define VIC1_VECTCNTL13 (volatile ULONG *)(VIC1_BASE + 0x0234)
#define VIC1_VECTCNTL14 (volatile ULONG *)(VIC1_BASE + 0x0238)
#define VIC1_VECTCNTL15 (volatile ULONG *)(VIC1_BASE + 0x023C)
#define VIC1_ITCR (volatile ULONG *)(VIC1_BASE + 0x0300)
#define VIC1_ITIP1 (volatile ULONG *)(VIC1_BASE + 0x0304)
#define VIC1_ITIP2 (volatile ULONG *)(VIC1_BASE + 0x0308)
#define VIC1_ITOP1 (volatile ULONG *)(VIC1_BASE + 0x030C)
#define VIC1_ITOP2 (volatile ULONG *)(VIC1_BASE + 0x0310)
#define VIC1_PERIPHID0 (volatile ULONG *)(VIC1_BASE + 0x0FE0)
#define VIC1_PERIPHID1 (volatile ULONG *)(VIC1_BASE + 0x0FE4)
#define VIC1_PERIPHID2 (volatile ULONG *)(VIC1_BASE + 0x0FE8)
#define VIC1_PERIPHID3 (volatile ULONG *)(VIC1_BASE + 0x0FEC)
#define VIC1_CELLID0 (volatile ULONG *)(VIC1_BASE + 0x0FF0)
#define VIC1_CELLID1 (volatile ULONG *)(VIC1_BASE + 0x0FF4)
#define VIC1_CELLID2 (volatile ULONG *)(VIC1_BASE + 0x0FF8)
#define VIC1_CELLID3 (volatile ULONG *)(VIC1_BASE + 0x0FFC)
#define VIC2_IRQSTATUS (volatile ULONG *)(VIC2_BASE + 0x0000)
#define VIC2_FIQSTATUS (volatile ULONG *)(VIC2_BASE + 0x0004)
#define VIC2_RAWINTR (volatile ULONG *)(VIC2_BASE + 0x0008)
#define VIC2_INTSELECT (volatile ULONG *)(VIC2_BASE + 0x000C)
#define VIC2_INTENABLE (volatile ULONG *)(VIC2_BASE + 0x0010)
#define VIC2_INTCLEAR (volatile ULONG *)(VIC2_BASE + 0x0014)
#define VIC2_SOFTINT (volatile ULONG *)(VIC2_BASE + 0x0018)
#define VIC2_SOFTINTCLEAR (volatile ULONG *)(VIC2_BASE + 0x001C)
#define VIC2_PROTECTION (volatile ULONG *)(VIC2_BASE + 0x0020)
#define VIC2_VECTCURADDR (volatile ULONG *)(VIC2_BASE + 0x0030)
#define VIC2_VECTDEFAULT (volatile ULONG *)(VIC2_BASE + 0x0034)
#define VIC2_VECTADDR0 (volatile ULONG *)(VIC2_BASE + 0x0100)
#define VIC2_VECTADDR1 (volatile ULONG *)(VIC2_BASE + 0x0104)
#define VIC2_VECTADDR2 (volatile ULONG *)(VIC2_BASE + 0x0108)
#define VIC2_VECTADDR3 (volatile ULONG *)(VIC2_BASE + 0x010C)
#define VIC2_VECTADDR4 (volatile ULONG *)(VIC2_BASE + 0x0110)
#define VIC2_VECTADDR5 (volatile ULONG *)(VIC2_BASE + 0x0114)
#define VIC2_VECTADDR6 (volatile ULONG *)(VIC2_BASE + 0x0118)
#define VIC2_VECTADDR7 (volatile ULONG *)(VIC2_BASE + 0x011C)
#define VIC2_VECTADDR8 (volatile ULONG *)(VIC2_BASE + 0x0120)
#define VIC2_VECTADDR9 (volatile ULONG *)(VIC2_BASE + 0x0124)
#define VIC2_VECTADDR10 (volatile ULONG *)(VIC2_BASE + 0x0128)
#define VIC2_VECTADDR11 (volatile ULONG *)(VIC2_BASE + 0x012C)
#define VIC2_VECTADDR12 (volatile ULONG *)(VIC2_BASE + 0x0130)
#define VIC2_VECTADDR13 (volatile ULONG *)(VIC2_BASE + 0x0134)
#define VIC2_VECTADDR14 (volatile ULONG *)(VIC2_BASE + 0x0138)
#define VIC2_VECTADDR15 (volatile ULONG *)(VIC2_BASE + 0x013C)
#define VIC2_VECTCNTL0 (volatile ULONG *)(VIC2_BASE + 0x0200)
#define VIC2_VECTCNTL1 (volatile ULONG *)(VIC2_BASE + 0x0204)
#define VIC2_VECTCNTL2 (volatile ULONG *)(VIC2_BASE + 0x0208)
#define VIC2_VECTCNTL3 (volatile ULONG *)(VIC2_BASE + 0x020C)
#define VIC2_VECTCNTL4 (volatile ULONG *)(VIC2_BASE + 0x0210)
#define VIC2_VECTCNTL5 (volatile ULONG *)(VIC2_BASE + 0x0214)
#define VIC2_VECTCNTL6 (volatile ULONG *)(VIC2_BASE + 0x0218)
#define VIC2_VECTCNTL7 (volatile ULONG *)(VIC2_BASE + 0x021C)
#define VIC2_VECTCNTL8 (volatile ULONG *)(VIC2_BASE + 0x0220)
#define VIC2_VECTCNTL9 (volatile ULONG *)(VIC2_BASE + 0x0224)
#define VIC2_VECTCNTL10 (volatile ULONG *)(VIC2_BASE + 0x0228)
#define VIC2_VECTCNTL11 (volatile ULONG *)(VIC2_BASE + 0x022C)
#define VIC2_VECTCNTL12 (volatile ULONG *)(VIC2_BASE + 0x0230)
#define VIC2_VECTCNTL13 (volatile ULONG *)(VIC2_BASE + 0x0234)
#define VIC2_VECTCNTL14 (volatile ULONG *)(VIC2_BASE + 0x0238)
#define VIC2_VECTCNTL15 (volatile ULONG *)(VIC2_BASE + 0x023C)
#define VIC2_ITCR (volatile ULONG *)(VIC2_BASE + 0x0300)
#define VIC2_ITIP1 (volatile ULONG *)(VIC2_BASE + 0x0304)
#define VIC2_ITIP2 (volatile ULONG *)(VIC2_BASE + 0x0308)
#define VIC2_ITOP1 (volatile ULONG *)(VIC2_BASE + 0x030C)
#define VIC2_ITOP2 (volatile ULONG *)(VIC2_BASE + 0x0310)
#define VIC2_PERIPHID0 (volatile ULONG *)(VIC2_BASE + 0x0FE0)
#define VIC2_PERIPHID1 (volatile ULONG *)(VIC2_BASE + 0x0FE4)
#define VIC2_PERIPHID2 (volatile ULONG *)(VIC2_BASE + 0x0FE8)
#define VIC2_PERIPHID3 (volatile ULONG *)(VIC2_BASE + 0x0FEC)
#define VIC2_CELLID0 (volatile ULONG *)(VIC2_BASE + 0x0FF0)
#define VIC2_CELLID1 (volatile ULONG *)(VIC2_BASE + 0x0FF4)
#define VIC2_CELLID2 (volatile ULONG *)(VIC2_BASE + 0x0FF8)
#define VIC2_CELLID3 (volatile ULONG *)(VIC2_BASE + 0x0FFC)
//
// Vic protection register definitions.
//
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