hwdefs.h

ARM下加一个硬件驱动比较复杂

//**********************************************************************
//                                                                      
// Filename: hwdefs.h
//                                                                      
// Description: Contains the registers and bit fields for the EP931x 
// on chip peripherals.
//
// THIS CODE AND INFORMATION IS PROVIDED "AS IS" WITHOUT WARRANTY OF
// ANY KIND, EITHER EXPRESSED OR IMPLIED, INCLUDING BUT NOT LIMITED TO
// THE IMPLIED WARRANTIES OF MERCHANTABILITY AND/OR FITNESS FOR A
// PARTICULAR PURPOSE.
//
// Use of this source code is subject to the terms of the Cirrus end-user
// license agreement (EULA) under which you licensed this SOFTWARE PRODUCT.
// If you did not accept the terms of the EULA, you are not authorized to 
// use this source code. For a copy of the EULA, please see the 
// EULA.RTF on your install media.
//
// Copyright(c) Cirrus Logic Corporation 2002, All Rights Reserved                       
//                                                                      
//**********************************************************************

#ifndef _H_HWDEFS
#define _H_HWDEFS
#include "memorymap.h"

//
// DMA 
//
#define DMA_BASE                    (VIRTUAL_SYSTEM_ASIC_REGS_BASE + 0x00000000)
#define DMA_M2P0_TX_BASE            ((volatile ULONG *) (DMA_BASE + 0x0000))
#define DMA_M2P1_RX_BASE            ((volatile ULONG *) (DMA_BASE + 0x0040))
#define DMA_M2P2_TX_BASE            ((volatile ULONG *) (DMA_BASE + 0x0080))
#define DMA_M2P3_RX_BASE            ((volatile ULONG *) (DMA_BASE + 0x00C0))
#define DMA_M2P4_TX_BASE            ((volatile ULONG *) (DMA_BASE + 0x0240))
#define DMA_M2P5_RX_BASE            ((volatile ULONG *) (DMA_BASE + 0x0200))
#define DMA_M2P6_TX_BASE            ((volatile ULONG *) (DMA_BASE + 0x02C0))
#define DMA_M2P7_RX_BASE            ((volatile ULONG *) (DMA_BASE + 0x0280))
#define DMA_M2P8_TX_BASE            ((volatile ULONG *) (DMA_BASE + 0x0340))
#define DMA_M2P9_RX_BASE            ((volatile ULONG *) (DMA_BASE + 0x0300))
#define DMA_M2M0_BASE               ((volatile ULONG *) (DMA_BASE + 0x0100))
#define DMA_M2M1_BASE               ((volatile ULONG *) (DMA_BASE + 0x0140))
                                    
#define M2P_CTRL                    0x00
#define M2P_INT                     0x04
#define M2P_PPALLOC                 0x08
#define M2P_STATUS                  0x0C
#define M2P_REMAIN                  0x14
#define M2P_MAXCNT0                 0x20
#define M2P_BASE0                   0x24
#define M2P_CURRENT0                0x28
#define M2P_MAXCNT1                 0x30
#define M2P_BASE1                   0x34
#define M2P_CURRENT1                0x38

#define M2M_CTRL                    0x00
#define M2M_INT                     0x04
#define M2M_STATUS                  0x0C
#define M2M_BCR0                    0x10            
#define M2M_BCR1                    0x14
#define M2M_SAR_BASE0               0x18
#define M2M_SAR_BASE1               0x1C
#define M2M_SAR_CURRENT0            0x24
#define M2M_SAR_CURRENT1            0x28
#define M2M_DAR_BASE0               0x2C
#define M2M_DAR_BASE1               0x30
#define M2M_DAR_CURRENT0            0x34
#define M2M_DAR_CURRENT1            0x3C


//
// Memory to peripheral DMA Control 
//
#define M2P_CTRL_STALLINTEN         0x00000001
#define M2P_CTRL_NFBINTEN           0x00000002
#define M2P_CTRL_CHERRORINTEN       0x00000008
#define M2P_CTRL_ENABLE             0x00000010
#define M2P_CTRL_ABORT              0x00000020
#define M2P_CTRL_ICE                0x00000040


//
// DMA Perhiperal Port allocation register.
//
#define PRALLOC_MASK                0x0000000F
#define PRALLOC_I2S1                0x00000000
#define PRALLOC_I2S2                0x00000001
#define PRALLOC_AAC1                0x00000002
#define PRALLOC_AAC2                0x00000003
#define PRALLOC_AAC3                0x00000004
#define PRALLOC_I2S3                0x00000005
#define PRALLOC_UART1               0x00000006
#define PRALLOC_UART2               0x00000007
#define PRALLOC_UART3               0x00000008
#define PRALLOC_IRDA                0x00000009

//
// Memory to Perphiral DMA interrupt register.
//
#define M2P_INT_STALLINT            0x00000001
#define M2P_INT_NFBINT              0x00000002
#define M2P_INT_CHERRORINT          0x00000008


//
// Memory to Peripheral DMA status register.
//
#define M2P_STATUS_STALL            0x00000001
#define M2P_STATUS_NFB              0x00000002
#define M2P_STATUS_CHERROR          0x00000008
#define M2P_STATUS_CURRSTATE_MASK   0x00000030
#define M2P_STATUS_CURRSTATE_IDLE   0x00000000
#define M2P_STATUS_CURRSTATE_STALL  0x00000010
#define M2P_STATUS_CURRSTATE_ON     0x00000020
#define M2P_STATUS_CURRSTATE_NEXT   0x00000030
#define M2P_STATUS_NEXTBUFFER       0x00000040
#define M2P_STATUS_BYTES_MASK       0x00000F80

//
// Memory to Peripheral DMA Remain register.
//
#define REMAIN_MASK                 0x0000FFFF

//
// Memory to Peripheral DMA Max Byte count 
//
#define MAXCNTX_MASK                0x0000FFFF

//
// Memory to Peripheral  DMA base address Register
//
#define BASEX_MASK                  0xFFFFFFFF


//
// Memory to Peripheral DMA current Address Register
//
#define CURRENTX_MASK               0xFFFFFFFF


//
// Memory to Memory DMA control
//
#define M2M_CTRL_STALLINTEN         0x00000001
#define M2M_CTRL_SCT                0x00000002
#define M2M_CTRL_DONEINTEN          0x00000004
#define M2M_CTRL_ENABLE             0x00000008
#define M2M_CTRL_START              0x00000010
#define M2M_CTRL_BWC_MASK           0x000001E0
#define M2M_CTRL_BWC_FULLTRANS      0x00000000
#define M2M_CTRL_BWC_16BYTES        0x00000020
#define M2M_CTRL_BWC_32BYTES        0x000000A0
#define M2M_CTRL_BWC_64BYTES        0x000000c0
#define M2M_CTRL_BWC_128BYTES       0x000000e0
#define M2M_CTRL_BWC_256BYTES       0x00000100
#define M2M_CTRL_BWC_512BYTES       0x00000120
#define M2M_CTRL_BWC_1024BYTES      0x00000140
#define M2M_CTRL_BWC_2048BYTES      0x00000160
#define M2M_CTRL_BWC_4096BYTES      0x00000180
#define M2M_CTRL_BWC_8192BYTES      0x000001a0
#define M2M_CTRL_BWC_16384BYTES     0x000001c0
#define M2M_CTRL_BWC_32768BYTES     0x000001e0
#define M2M_CTRL_PW_MASK            0x00000600
#define M2M_CTRL_PW_BYTE            0x00000000
#define M2M_CTRL_PW_HALFWORD        0x00000200
#define M2M_CTRL_PW_WORD            0x00000400
#define M2M_CTRL_DAH                0x00000800
#define M2M_CTRL_SAH                0x00001000
#define M2M_CTRL_TM_MASK            0x00006000
#define M2M_CTRL_TM_SOFTINIT        0x00000000
#define M2M_CTRL_TM_HARDINITM2P     0x00002000
#define M2M_CTRL_TM_HARDINITP2M     0x00004000
#define M2M_CTRL_ETDP_MASK          0x00018000
#define M2M_CTRL_ETDP_ALOW_INPUT    0x00000000
#define M2M_CTRL_ETDP_AHIGH_INPUT   0x00008000
#define M2M_CTRL_ETDP_ALOW_OUTPUT   0x00010000
#define M2M_CTRL_ETDP_AHIGH_OUTPUT  0x00018000
#define M2M_CTRL_DACKP_ACTIVEHIGH   0x00020000
#define M2M_CTRL_DREQP_MASK         0x00180000
#define M2M_CTRL_DREQP_LOWLEVEL     0x00000000
#define M2M_CTRL_DREQP_HIGHLEVEL    0x00080000
#define M2M_CTRL_DREQP_LOWEDGE      0x00100000
#define M2M_CTRL_DREQP_HIGHEDGE     0x00180000
#define M2M_CTRL_NFBINTEN           0x00200000
#define M2M_CTRL_RSS_MASK           0x00C00000
#define M2M_CTRL_RSS_EXTDREQ        0x00000000
#define M2M_CTRL_RSS_INTSSPRX       0x00400000
#define M2M_CTRL_RSS_INTSSPTX       0x00800000
#define M2M_CTRL_RSS_INTIDE         0x00C00000
#define M2M_CTRL_NO_HDSK            0x01000000
#define M2M_CTRL_PWSC_MASK          0xFE000000
#define M2M_CTRL_PWSC_SHIFT         25

//
// Memory to memory DMA interrupt register definitions.
//
#define M2M_INTERRUPT_STALLIN       0x00000001
#define M2M_INTERRUPT_DONEINT       0x00000002
#define M2M_INTERRUPT_NFBINT        0x00000004

//
// Memory to memory DMA status definitions.
//
#define M2M_STATUS_STALL            0x00000001
#define M2P_STATUS_CURSTATE_MASK    0x0000000E
#define M2P_STATUS_CURSTATE_IDLE    0x00000000
#define M2P_STATUS_CURSTATE_STALL   0x00000002
#define M2P_STATUS_CURSTATE_MEMRD   0x00000004
#define M2P_STATUS_CURSTATE_MEMWR   0x00000006
#define M2M_STATUS_CURSTATE_BMCWAIT 0x00000008
#define M2P_STATUS_BUFFTATE_MASK    0x00000030
#define M2M_STATUS_BUFFSTATE_NOBUF  0x00000000
#define M2M_STATUS_BUFFSTATE_BUFON  0x00000010
#define M2M_STATUS_BUFFSTATE_NEXT   0x00000020
#define M2M_STATUS_DONE             0x00000040
#define M2M_STATUS_TCS0             0x00000080
#define M2M_STATUS_TCS1             0x00000100
#define M2M_STATUS_ETOS0            0x00000200
#define M2M_STATUS_ETOS1            0x00000400
#define M2M_STATUS_NFB              0x00000800
#define M2M_STATUS_NB               0x00001000
#define M2M_STATUS_DREQS            0x00002000

//
// Memory to Memory DMA BCRx
//
#define M2M_BCR_MASK                0x0000FFFF


//
// Ethernet 
// TODO bit patters.
//
#define ETHERNET_BASE               (VIRTUAL_SYSTEM_ASIC_REGS_BASE + 0x00010000)

//
// Raster Registers.
//
#define RASTER_BASE                 (VIRTUAL_SYSTEM_ASIC_REGS_BASE + 0x30000)
#define RASTER_VLINESTOTAL          ((volatile ULONG *) (RASTER_BASE + 0x000) )
#define RASTER_VSYNCSTRTSTOP        ((volatile ULONG *) (RASTER_BASE + 0x004) )
#define RASTER_VACTIVESTRTSTOP      ((volatile ULONG *) (RASTER_BASE + 0x008) )
#define RASTER_VCLKSTRTSTOP         ((volatile ULONG *) (RASTER_BASE + 0x00C) )
#define RASTER_HCLKSTOTAL           ((volatile ULONG *) (RASTER_BASE + 0x010) )
#define RASTER_HSYNCSTRTSTOP        ((volatile ULONG *) (RASTER_BASE + 0x014) )
#define RASTER_HACTIVESTRTSTOP      ((volatile ULONG *) (RASTER_BASE + 0x018) )
#define RASTER_HCLKSTRTSTOP         ((volatile ULONG *) (RASTER_BASE + 0x01C) )
#define RASTER_BRIGHTNESS           ((volatile ULONG *) (RASTER_BASE + 0x020) )
#define RASTER_VIDEOATTRIBS         ((volatile ULONG *) (RASTER_BASE + 0x024) )
#define RASTER_VIDSCRNPAGE          ((volatile ULONG *) (RASTER_BASE + 0x028) )
#define RASTER_VIDSCRNHPG           ((volatile ULONG *) (RASTER_BASE + 0x02C) )
#define RASTER_SCRNLINES            ((volatile ULONG *) (RASTER_BASE + 0x030) )
#define RASTER_LINELENGTH           ((volatile ULONG *) (RASTER_BASE + 0x034) )
#define RASTER_VLINESTEP            ((volatile ULONG *) (RASTER_BASE + 0x038) )
#define RASTER_LINECARRY            ((volatile ULONG *) (RASTER_BASE + 0x03C) )
#define RASTER_BLINKRATE            ((volatile ULONG *) (RASTER_BASE + 0x040) )
#define RASTER_BLINKMASK            ((volatile ULONG *) (RASTER_BASE + 0x044) )
#define RASTER_BLINKPATRN           ((volatile ULONG *) (RASTER_BASE + 0x048) )
#define RASTER_PATTRNMASK           ((volatile ULONG *) (RASTER_BASE + 0x04C) )
#define RASTER_BG_OFFSET            ((volatile ULONG *) (RASTER_BASE + 0x050) )
#define RASTER_PIXELMODE            ((volatile ULONG *) (RASTER_BASE + 0x054) )
#define RASTER_PARLLIFOUT           ((volatile ULONG *) (RASTER_BASE + 0x058) )
#define RASTER_PARLLIFIN            ((volatile ULONG *) (RASTER_BASE + 0x05C) )
#define RASTER_CURSOR_ADR_START     ((volatile ULONG *) (RASTER_BASE + 0x060) )
#define RASTER_CURSOR_ADR_RESET     ((volatile ULONG *) (RASTER_BASE + 0x064) )
#define RASTER_CURSORSIZE           ((volatile ULONG *) (RASTER_BASE + 0x068) )
#define RASTER_CURSORCOLOR1         ((volatile ULONG *) (RASTER_BASE + 0x06C) )
#define RASTER_CURSORCOLOR2         ((volatile ULONG *) (RASTER_BASE + 0x070) )
#define RASTER_CURSORXYLOC          ((volatile ULONG *) (RASTER_BASE + 0x074) )
#define RASTER_CURSOR_DSCAN_LH_YLOC ((volatile ULONG *) (RASTER_BASE + 0x078) )
#define RASTER_REALITI_SWLOCK       ((volatile ULONG *) (RASTER_BASE + 0x07C) )
#define RASTER_GRAYSCALE_LUT        ((volatile ULONG *) (RASTER_BASE + 0x080) )
#define RASTER_SIGVAL               ((volatile ULONG *) (RASTER_BASE + 0x200) )
#define RASTER_SIGCTL               ((volatile ULONG *) (RASTER_BASE + 0x204) )
#define RASTER_VSIGSTRTSTOP         ((volatile ULONG *) (RASTER_BASE + 0x208) )
#define RASTER_HSIGSTRTSTOP         ((volatile ULONG *) (RASTER_BASE + 0x20C) )
#define RASTER_SIGCLR               ((volatile ULONG *) (RASTER_BASE + 0x210) )
#define RASTER_ACRATE               ((volatile ULONG *) (RASTER_BASE + 0x214) )
#define RASTER_LUTCONT              ((volatile ULONG *) (RASTER_BASE + 0x218) )
#define RASTER_CURSOR_BLINK1        ((volatile ULONG *) (RASTER_BASE + 0x21C) )
#define RASTER_CURSOR_BLINK2        ((volatile ULONG *) (RASTER_BASE + 0x220) )
#define RASTER_CURSOR_BLINK         ((volatile ULONG *) (RASTER_BASE + 0x224) )