dds_4k.v

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module DDS_4K( Din,
				WR,
				CS,
			   CLK,         //40MHz
			  Addr,
			  Aout
              );

input [7:0] Din;
input WR;
input CS;
input CLK;
input [1:0] Addr;
output [11:0] Aout;

reg[31:0] ACC;           //0.01Hz StepLength
reg[27:0] K;             //2MHz Most 

//wire CLK_4;

assign Aout=ACC[31:20];

//fp_10 fp_10_1(CLK,CLK_4);


always@(posedge CLK)
	begin
	  if((!CS)&(!WR))
		begin
			case(Addr)
				0:K[7:0]<=Din;
				1:K[15:8]<=Din;
				2:K[23:16]<=Din;
				3:K[27:24]<=Din[3:0];
			endcase
		end
	end

always@(posedge CLK)
	begin
	  ACC<=ACC+K;
	end
	
endmodule