ad9851_2007.fit.eqn

计算实用教程adadad9851实用教程

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--D1_WCK is module_9851:inst2|WCK at LC_X11_Y8_N4
--operation mode is normal

D1_WCK_lut_out = D1L403 & (!D1L468 & D1L488) # !D1L403 & D1L399;
D1_WCK = DFFEAS(D1_WCK_lut_out, GLOBAL(B1_Cout), VCC, , C1L2, , , , );


--D1_FQD is module_9851:inst2|FQD at LC_X12_Y10_N1
--operation mode is normal

D1_FQD_lut_out = D1L405 # D1L410 & (D1L412 # D1L411);
D1_FQD = DFFEAS(D1_FQD_lut_out, GLOBAL(B1_Cout), VCC, , C1L2, , , , );


--D1_RST is module_9851:inst2|RST at LC_X12_Y10_N3
--operation mode is normal

D1_RST_lut_out = D1L391 & (D1L393 & !D1_Count1[2] # !D1L393 & (D1_RST));
D1_RST = DFFEAS(D1_RST_lut_out, GLOBAL(B1_Cout), VCC, , C1L2, , , , );


--K1_TIAOZHIBO is PSK_ASK:inst12|TIAOZHIBO at LC_X11_Y15_N8
--operation mode is normal

K1_TIAOZHIBO_lut_out = D1L217 & K1_TIAOZHIBO # !D1L217 & (K1_code);
K1_TIAOZHIBO = DFFEAS(K1_TIAOZHIBO_lut_out, L1_Cout, VCC, , , , , , );


--C1L6 is ASIC74138:inst1|CSout[5]~74 at LC_X22_Y13_N4
--operation mode is normal

C1L6 = P2[5] # !P2[7] # !P2[6] # !P2[4];


--HB1_q_a[4] is ScanKey:inst29|altsyncram:reduce_or_rtl_0|altsyncram_d9l:auto_generated|q_a[4] at M4K_X17_Y1
--RAM Block Operation Mode: ROM
--Port A Depth: 512, Port A Width: 5
--Port A Logical Depth: 512, Port A Logical Width: 5
--Port A Input: Registered, Port A Output: Un-registered
HB1_q_a[4]_PORT_A_address = BUS(T1_KR_temp[0], T1_KR_temp[1], T1_KR_temp[2], T1_KR_temp[3], T1_KR_temp[4], T1_KR_temp[5], T1_KC_temp[0], T1_KC_temp[1], T1_KC_temp[2]);
HB1_q_a[4]_PORT_A_address_reg = DFFE(HB1_q_a[4]_PORT_A_address, HB1_q_a[4]_clock_0, , , );
HB1_q_a[4]_clock_0 = GLOBAL(ALE);
HB1_q_a[4]_PORT_A_data_out = MEMORY(, , HB1_q_a[4]_PORT_A_address_reg, , , , , , HB1_q_a[4]_clock_0, , , , , );
HB1_q_a[4] = HB1_q_a[4]_PORT_A_data_out[0];

--HB1_q_a[3] is ScanKey:inst29|altsyncram:reduce_or_rtl_0|altsyncram_d9l:auto_generated|q_a[3] at M4K_X17_Y1
HB1_q_a[4]_PORT_A_address = BUS(T1_KR_temp[0], T1_KR_temp[1], T1_KR_temp[2], T1_KR_temp[3], T1_KR_temp[4], T1_KR_temp[5], T1_KC_temp[0], T1_KC_temp[1], T1_KC_temp[2]);
HB1_q_a[4]_PORT_A_address_reg = DFFE(HB1_q_a[4]_PORT_A_address, HB1_q_a[4]_clock_0, , , );
HB1_q_a[4]_clock_0 = GLOBAL(ALE);
HB1_q_a[4]_PORT_A_data_out = MEMORY(, , HB1_q_a[4]_PORT_A_address_reg, , , , , , HB1_q_a[4]_clock_0, , , , , );
HB1_q_a[3] = HB1_q_a[4]_PORT_A_data_out[4];

--HB1_q_a[2] is ScanKey:inst29|altsyncram:reduce_or_rtl_0|altsyncram_d9l:auto_generated|q_a[2] at M4K_X17_Y1
HB1_q_a[4]_PORT_A_address = BUS(T1_KR_temp[0], T1_KR_temp[1], T1_KR_temp[2], T1_KR_temp[3], T1_KR_temp[4], T1_KR_temp[5], T1_KC_temp[0], T1_KC_temp[1], T1_KC_temp[2]);
HB1_q_a[4]_PORT_A_address_reg = DFFE(HB1_q_a[4]_PORT_A_address, HB1_q_a[4]_clock_0, , , );
HB1_q_a[4]_clock_0 = GLOBAL(ALE);
HB1_q_a[4]_PORT_A_data_out = MEMORY(, , HB1_q_a[4]_PORT_A_address_reg, , , , , , HB1_q_a[4]_clock_0, , , , , );
HB1_q_a[2] = HB1_q_a[4]_PORT_A_data_out[3];

--HB1_q_a[1] is ScanKey:inst29|altsyncram:reduce_or_rtl_0|altsyncram_d9l:auto_generated|q_a[1] at M4K_X17_Y1
HB1_q_a[4]_PORT_A_address = BUS(T1_KR_temp[0], T1_KR_temp[1], T1_KR_temp[2], T1_KR_temp[3], T1_KR_temp[4], T1_KR_temp[5], T1_KC_temp[0], T1_KC_temp[1], T1_KC_temp[2]);
HB1_q_a[4]_PORT_A_address_reg = DFFE(HB1_q_a[4]_PORT_A_address, HB1_q_a[4]_clock_0, , , );
HB1_q_a[4]_clock_0 = GLOBAL(ALE);
HB1_q_a[4]_PORT_A_data_out = MEMORY(, , HB1_q_a[4]_PORT_A_address_reg, , , , , , HB1_q_a[4]_clock_0, , , , , );
HB1_q_a[1] = HB1_q_a[4]_PORT_A_data_out[2];

--HB1_q_a[0] is ScanKey:inst29|altsyncram:reduce_or_rtl_0|altsyncram_d9l:auto_generated|q_a[0] at M4K_X17_Y1
HB1_q_a[4]_PORT_A_address = BUS(T1_KR_temp[0], T1_KR_temp[1], T1_KR_temp[2], T1_KR_temp[3], T1_KR_temp[4], T1_KR_temp[5], T1_KC_temp[0], T1_KC_temp[1], T1_KC_temp[2]);
HB1_q_a[4]_PORT_A_address_reg = DFFE(HB1_q_a[4]_PORT_A_address, HB1_q_a[4]_clock_0, , , );
HB1_q_a[4]_clock_0 = GLOBAL(ALE);
HB1_q_a[4]_PORT_A_data_out = MEMORY(, , HB1_q_a[4]_PORT_A_address_reg, , , , , , HB1_q_a[4]_clock_0, , , , , );
HB1_q_a[0] = HB1_q_a[4]_PORT_A_data_out[1];


--A1L124 is rtl~374 at LC_X23_Y15_N5
--operation mode is normal

A1L124 = HB1_q_a[1] & (HB1_q_a[0]);


--A1L118 is rtl~0 at LC_X23_Y15_N6
--operation mode is normal

A1L118 = HB1_q_a[2] & HB1_q_a[4] & HB1_q_a[3] & A1L124;


--C1L3 is ASIC74138:inst1|CSout[3]~75 at LC_X23_Y13_N1
--operation mode is normal

C1L3 = P2[6] # !P2[5] # !P2[4] # !P2[7];


--R1_COV is max195:inst21|COV at LC_X28_Y14_N1
--operation mode is normal

R1_COV_lut_out = R1L62 & (R1L63 & R1_count[1] # !R1L63 & (R1_COV)) # !R1L62 & (R1_COV);
R1_COV = DFFEAS(R1_COV_lut_out, GLOBAL(B4_Cout), VCC, , , , , , );


--R1_CLK_MAX195 is max195:inst21|CLK_MAX195 at LC_X28_Y14_N4
--operation mode is normal

R1_CLK_MAX195_lut_out = R1_count[1];
R1_CLK_MAX195 = DFFEAS(R1_CLK_MAX195_lut_out, GLOBAL(B4_Cout), VCC, , , , , , );


--V1_CS is max542:inst31|CS at LC_X12_Y17_N3
--operation mode is normal

V1_CS_lut_out = V1L45 & (V1_count[2] # !V1_count[1]) # !V1L45 & (V1_CS);
V1_CS = DFFEAS(V1_CS_lut_out, GLOBAL(B4_Cout), VCC, , , , , , );


--V1_SCLK is max542:inst31|SCLK at LC_X12_Y17_N8
--operation mode is normal

V1_SCLK_lut_out = V1_count[0] & (V1L50 & (V1L52) # !V1L50 & V1L46) # !V1_count[0] & (V1L50);
V1_SCLK = DFFEAS(V1_SCLK_lut_out, GLOBAL(B4_Cout), VCC, , , , , , );


--V1_D_out is max542:inst31|D_out at LC_X13_Y17_N3
--operation mode is normal

V1_D_out_lut_out = V1_count[0] & V1_D_out # !V1_count[0] & (V1L21 # V1_D_out & V1L22);
V1_D_out = DFFEAS(V1_D_out_lut_out, GLOBAL(B4_Cout), VCC, , , , , , );


--R1_INT is max195:inst21|INT at LC_X28_Y14_N3
--operation mode is normal

R1_INT_lut_out = R1L61 & (R1_count[3] & (R1_count[1] # R1_INT) # !R1_count[3] & !R1_count[1]) # !R1L61 & (R1_INT);
R1_INT = DFFEAS(R1_INT_lut_out, GLOBAL(B4_Cout), VCC, , , , , , );


--GB1_q_a[7] is lpm_rom1:inst17|altsyncram:altsyncram_component|altsyncram_qbs:auto_generated|q_a[7] at M4K_X17_Y14
--RAM Block Operation Mode: ROM
--Port A Depth: 4096, Port A Width: 1
--Port A Logical Depth: 4096, Port A Logical Width: 8
--Port A Input: Registered, Port A Output: Registered
GB1_q_a[7]_PORT_A_address = BUS(M1_ACC[20], M1_ACC[21], M1_ACC[22], M1_ACC[23], M1_ACC[24], M1_ACC[25], M1_ACC[26], M1_ACC[27], M1_ACC[28], M1_ACC[29], M1_ACC[30], M1_ACC[31]);
GB1_q_a[7]_PORT_A_address_reg = DFFE(GB1_q_a[7]_PORT_A_address, GB1_q_a[7]_clock_0, , , );
GB1_q_a[7]_clock_0 = GLOBAL(CLK);
GB1_q_a[7]_PORT_A_data_out = MEMORY(, , GB1_q_a[7]_PORT_A_address_reg, , , , , , GB1_q_a[7]_clock_0, , , , , );
GB1_q_a[7]_PORT_A_data_out_reg = DFFE(GB1_q_a[7]_PORT_A_data_out, GB1_q_a[7]_clock_0, , , );
GB1_q_a[7] = GB1_q_a[7]_PORT_A_data_out_reg[0];


--GB1_q_a[6] is lpm_rom1:inst17|altsyncram:altsyncram_component|altsyncram_qbs:auto_generated|q_a[6] at M4K_X17_Y9
--RAM Block Operation Mode: ROM
--Port A Depth: 4096, Port A Width: 1
--Port A Logical Depth: 4096, Port A Logical Width: 8
--Port A Input: Registered, Port A Output: Registered
GB1_q_a[6]_PORT_A_address = BUS(M1_ACC[20], M1_ACC[21], M1_ACC[22], M1_ACC[23], M1_ACC[24], M1_ACC[25], M1_ACC[26], M1_ACC[27], M1_ACC[28], M1_ACC[29], M1_ACC[30], M1_ACC[31]);
GB1_q_a[6]_PORT_A_address_reg = DFFE(GB1_q_a[6]_PORT_A_address, GB1_q_a[6]_clock_0, , , );
GB1_q_a[6]_clock_0 = GLOBAL(CLK);
GB1_q_a[6]_PORT_A_data_out = MEMORY(, , GB1_q_a[6]_PORT_A_address_reg, , , , , , GB1_q_a[6]_clock_0, , , , , );
GB1_q_a[6]_PORT_A_data_out_reg = DFFE(GB1_q_a[6]_PORT_A_data_out, GB1_q_a[6]_clock_0, , , );
GB1_q_a[6] = GB1_q_a[6]_PORT_A_data_out_reg[0];


--GB1_q_a[5] is lpm_rom1:inst17|altsyncram:altsyncram_component|altsyncram_qbs:auto_generated|q_a[5] at M4K_X17_Y10
--RAM Block Operation Mode: ROM
--Port A Depth: 4096, Port A Width: 1
--Port A Logical Depth: 4096, Port A Logical Width: 8
--Port A Input: Registered, Port A Output: Registered
GB1_q_a[5]_PORT_A_address = BUS(M1_ACC[20], M1_ACC[21], M1_ACC[22], M1_ACC[23], M1_ACC[24], M1_ACC[25], M1_ACC[26], M1_ACC[27], M1_ACC[28], M1_ACC[29], M1_ACC[30], M1_ACC[31]);
GB1_q_a[5]_PORT_A_address_reg = DFFE(GB1_q_a[5]_PORT_A_address, GB1_q_a[5]_clock_0, , , );
GB1_q_a[5]_clock_0 = GLOBAL(CLK);
GB1_q_a[5]_PORT_A_data_out = MEMORY(, , GB1_q_a[5]_PORT_A_address_reg, , , , , , GB1_q_a[5]_clock_0, , , , , );
GB1_q_a[5]_PORT_A_data_out_reg = DFFE(GB1_q_a[5]_PORT_A_data_out, GB1_q_a[5]_clock_0, , , );
GB1_q_a[5] = GB1_q_a[5]_PORT_A_data_out_reg[0];


--GB1_q_a[4] is lpm_rom1:inst17|altsyncram:altsyncram_component|altsyncram_qbs:auto_generated|q_a[4] at M4K_X17_Y8
--RAM Block Operation Mode: ROM
--Port A Depth: 4096, Port A Width: 1
--Port A Logical Depth: 4096, Port A Logical Width: 8
--Port A Input: Registered, Port A Output: Registered
GB1_q_a[4]_PORT_A_address = BUS(M1_ACC[20], M1_ACC[21], M1_ACC[22], M1_ACC[23], M1_ACC[24], M1_ACC[25], M1_ACC[26], M1_ACC[27], M1_ACC[28], M1_ACC[29], M1_ACC[30], M1_ACC[31]);
GB1_q_a[4]_PORT_A_address_reg = DFFE(GB1_q_a[4]_PORT_A_address, GB1_q_a[4]_clock_0, , , );
GB1_q_a[4]_clock_0 = GLOBAL(CLK);
GB1_q_a[4]_PORT_A_data_out = MEMORY(, , GB1_q_a[4]_PORT_A_address_reg, , , , , , GB1_q_a[4]_clock_0, , , , , );
GB1_q_a[4]_PORT_A_data_out_reg = DFFE(GB1_q_a[4]_PORT_A_data_out, GB1_q_a[4]_clock_0, , , );
GB1_q_a[4] = GB1_q_a[4]_PORT_A_data_out_reg[0];


--GB1_q_a[3] is lpm_rom1:inst17|altsyncram:altsyncram_component|altsyncram_qbs:auto_generated|q_a[3] at M4K_X17_Y15
--RAM Block Operation Mode: ROM
--Port A Depth: 4096, Port A Width: 1
--Port A Logical Depth: 4096, Port A Logical Width: 8
--Port A Input: Registered, Port A Output: Registered
GB1_q_a[3]_PORT_A_address = BUS(M1_ACC[20], M1_ACC[21], M1_ACC[22], M1_ACC[23], M1_ACC[24], M1_ACC[25], M1_ACC[26], M1_ACC[27], M1_ACC[28], M1_ACC[29], M1_ACC[30], M1_ACC[31]);
GB1_q_a[3]_PORT_A_address_reg = DFFE(GB1_q_a[3]_PORT_A_address, GB1_q_a[3]_clock_0, , , );
GB1_q_a[3]_clock_0 = GLOBAL(CLK);
GB1_q_a[3]_PORT_A_data_out = MEMORY(, , GB1_q_a[3]_PORT_A_address_reg, , , , , , GB1_q_a[3]_clock_0, , , , , );
GB1_q_a[3]_PORT_A_data_out_reg = DFFE(GB1_q_a[3]_PORT_A_data_out, GB1_q_a[3]_clock_0, , , );
GB1_q_a[3] = GB1_q_a[3]_PORT_A_data_out_reg[0];


--GB1_q_a[2] is lpm_rom1:inst17|altsyncram:altsyncram_component|altsyncram_qbs:auto_generated|q_a[2] at M4K_X17_Y12
--RAM Block Operation Mode: ROM
--Port A Depth: 4096, Port A Width: 1
--Port A Logical Depth: 4096, Port A Logical Width: 8
--Port A Input: Registered, Port A Output: Registered
GB1_q_a[2]_PORT_A_address = BUS(M1_ACC[20], M1_ACC[21], M1_ACC[22], M1_ACC[23], M1_ACC[24], M1_ACC[25], M1_ACC[26], M1_ACC[27], M1_ACC[28], M1_ACC[29], M1_ACC[30], M1_ACC[31]);
GB1_q_a[2]_PORT_A_address_reg = DFFE(GB1_q_a[2]_PORT_A_address, GB1_q_a[2]_clock_0, , , );
GB1_q_a[2]_clock_0 = GLOBAL(CLK);
GB1_q_a[2]_PORT_A_data_out = MEMORY(, , GB1_q_a[2]_PORT_A_address_reg, , , , , , GB1_q_a[2]_clock_0, , , , , );
GB1_q_a[2]_PORT_A_data_out_reg = DFFE(GB1_q_a[2]_PORT_A_data_out, GB1_q_a[2]_clock_0, , , );
GB1_q_a[2] = GB1_q_a[2]_PORT_A_data_out_reg[0];


--GB1_q_a[1] is lpm_rom1:inst17|altsyncram:altsyncram_component|altsyncram_qbs:auto_generated|q_a[1] at M4K_X17_Y11
--RAM Block Operation Mode: ROM
--Port A Depth: 4096, Port A Width: 1
--Port A Logical Depth: 4096, Port A Logical Width: 8
--Port A Input: Registered, Port A Output: Registered
GB1_q_a[1]_PORT_A_address = BUS(M1_ACC[20], M1_ACC[21], M1_ACC[22], M1_ACC[23], M1_ACC[24], M1_ACC[25], M1_ACC[26], M1_ACC[27], M1_ACC[28], M1_ACC[29], M1_ACC[30], M1_ACC[31]);
GB1_q_a[1]_PORT_A_address_reg = DFFE(GB1_q_a[1]_PORT_A_address, GB1_q_a[1]_clock_0, , , );
GB1_q_a[1]_clock_0 = GLOBAL(CLK);
GB1_q_a[1]_PORT_A_data_out = MEMORY(, , GB1_q_a[1]_PORT_A_address_reg, , , , , , GB1_q_a[1]_clock_0, , , , , );
GB1_q_a[1]_PORT_A_data_out_reg = DFFE(GB1_q_a[1]_PORT_A_data_out, GB1_q_a[1]_clock_0, , , );
GB1_q_a[1] = GB1_q_a[1]_PORT_A_data_out_reg[0];


--GB1_q_a[0] is lpm_rom1:inst17|altsyncram:altsyncram_component|altsyncram_qbs:auto_generated|q_a[0] at M4K_X17_Y13
--RAM Block Operation Mode: ROM
--Port A Depth: 4096, Port A Width: 1
--Port A Logical Depth: 4096, Port A Logical Width: 8
--Port A Input: Registered, Port A Output: Registered
GB1_q_a[0]_PORT_A_address = BUS(M1_ACC[20], M1_ACC[21], M1_ACC[22], M1_ACC[23], M1_ACC[24], M1_ACC[25], M1_ACC[26], M1_ACC[27], M1_ACC[28], M1_ACC[29], M1_ACC[30], M1_ACC[31]);
GB1_q_a[0]_PORT_A_address_reg = DFFE(GB1_q_a[0]_PORT_A_address, GB1_q_a[0]_clock_0, , , );
GB1_q_a[0]_clock_0 = GLOBAL(CLK);
GB1_q_a[0]_PORT_A_data_out = MEMORY(, , GB1_q_a[0]_PORT_A_address_reg, , , , , , GB1_q_a[0]_clock_0, , , , , );
GB1_q_a[0]_PORT_A_data_out_reg = DFFE(GB1_q_a[0]_PORT_A_data_out, GB1_q_a[0]_clock_0, , , );
GB1_q_a[0] = GB1_q_a[0]_PORT_A_data_out_reg[0];


--D1_Dout[7] is module_9851:inst2|Dout[7] at LC_X13_Y11_N7
--operation mode is normal

D1_Dout[7]_lut_out = D1L423 & (D1L422 # D1L424 & D1L418) # !D1L423 & (D1L418);
D1_Dout[7] = DFFEAS(D1_Dout[7]_lut_out, GLOBAL(B1_Cout), VCC, , C1L2, , , , );


--D1_Dout[6] is module_9851:inst2|Dout[6] at LC_X12_Y11_N9
--operation mode is normal

D1_Dout[6]_lut_out = D1L74 & D1L430 & (!D1_Count1[3]) # !D1L74 & (D1L428);
D1_Dout[6] = DFFEAS(D1_Dout[6]_lut_out, GLOBAL(B1_Cout), VCC, , D1L85, , , , );


--D1_Dout[5] is module_9851:inst2|Dout[5] at LC_X12_Y11_N2
--operation mode is normal

D1_Dout[5]_lut_out = D1L74 & (D1L435 & !D1_Count1[3]) # !D1L74 & D1L433;
D1_Dout[5] = DFFEAS(D1_Dout[5]_lut_out, GLOBAL(B1_Cout), VCC, , D1L85, , , , );


--D1_Dout[4] is module_9851:inst2|Dout[4] at LC_X11_Y12_N0
--operation mode is normal

D1_Dout[4]_lut_out = D1L74 & !D1_Count1[3] & D1L440 # !D1L74 & (D1L438);
D1_Dout[4] = DFFEAS(D1_Dout[4]_lut_out, GLOBAL(B1_Cout), VCC, , D1L85, , , , );


--D1_Dout[3] is module_9851:inst2|Dout[3] at LC_X11_Y12_N9
--operation mode is normal

D1_Dout[3]_lut_out = D1L74 & !D1_Count1[3] & D1L445 # !D1L74 & (D1L443);
D1_Dout[3] = DFFEAS(D1_Dout[3]_lut_out, GLOBAL(B1_Cout), VCC, , D1L85, , , , );


--D1_Dout[2] is module_9851:inst2|Dout[2] at LC_X12_Y12_N5
--operation mode is normal

D1_Dout[2]_lut_out = D1L74 & !D1_Count1[3] & (D1L450) # !D1L74 & (D1L448);
D1_Dout[2] = DFFEAS(D1_Dout[2]_lut_out, GLOBAL(B1_Cout), VCC, , D1L85, , , , );


--D1_Dout[1] is module_9851:inst2|Dout[1] at LC_X12_Y12_N0
--operation mode is normal

D1_Dout[1]_lut_out = D1L74 & !D1_Count1[3] & (D1L455) # !D1L74 & (D1L453);
D1_Dout[1] = DFFEAS(D1_Dout[1]_lut_out, GLOBAL(B1_Cout), VCC, , D1L85, , , , );


--D1_Dout[0] is module_9851:inst2|Dout[0] at LC_X12_Y12_N8
--operation mode is normal

D1_Dout[0]_lut_out = D1L74 & (D1_Count1[3] # D1L460) # !D1L74 & (D1L458);
D1_Dout[0] = DFFEAS(D1_Dout[0]_lut_out, GLOBAL(B1_Cout), VCC, , D1L85, , , , );


--D1L468 is module_9851:inst2|add~2005 at LC_X12_Y8_N0
--operation mode is arithmetic

D1L468 = D1_Count3[0] $ !D1L217;

--D1L469 is module_9851:inst2|add~2007 at LC_X12_Y8_N0
--operation mode is arithmetic

D1L469_cout_0 = D1_Count3[0] & !D1L217;
D1L469 = CARRY(D1L469_cout_0);

--D1L470 is module_9851:inst2|add~2007COUT1_2106 at LC_X12_Y8_N0
--operation mode is arithmetic

D1L470_cout_1 = D1_Count3[0] & !D1L217;
D1L470 = CARRY(D1L470_cout_1);


--D1L471 is module_9851:inst2|add~2010 at LC_X12_Y9_N5
--operation mode is arithmetic

D1L471_carry_eqn = (!D1L479 & GND) # (D1L479 & VCC);
D1L471 = D1_Count2[4] $ (!D1L471_carry_eqn);

--D1L472 is module_9851:inst2|add~2012 at LC_X12_Y9_N5
--operation mode is arithmetic

D1L472_cout_0 = D1_Count2[4] & (!D1L479);
D1L472 = CARRY(D1L472_cout_0);

--D1L473 is module_9851:inst2|add~2012COUT1_2122 at LC_X12_Y9_N5
--operation mode is arithmetic

D1L473_cout_1 = D1_Count2[4] & (!D1L479);
D1L473 = CARRY(D1L473_cout_1);


--D1L474 is module_9851:inst2|add~2015 at LC_X12_Y9_N6
--operation mode is normal

D1L474_carry_eqn = (!D1L479 & D1L472) # (D1L479 & D1L473);
D1L474 = D1L474_carry_eqn $ D1_Count2[5];


--D1L475 is module_9851:inst2|add~2020 at LC_X12_Y9_N1
--operation mode is arithmetic

D1L475 = D1_Count2[0] $ A1L125;

--D1L476 is module_9851:inst2|add~2022 at LC_X12_Y9_N1
--operation mode is arithmetic

D1L476_cout_0 = D1_Count2[0] & A1L125;
D1L476 = CARRY(D1L476_cout_0);

--D1L477 is module_9851:inst2|add~2022COUT1_2117 at LC_X12_Y9_N1
--operation mode is arithmetic

D1L477_cout_1 = D1_Count2[0] & A1L125;
D1L477 = CARRY(D1L477_cout_1);


--D1L43 is module_9851:inst2|Decoder~1644 at LC_X13_Y9_N9
--operation mode is normal

D1L43 = !D1L474 & (!D1L475);


--D1L478 is module_9851:inst2|add~2025 at LC_X12_Y9_N4
--operation mode is arithmetic

D1L478 = D1_Count2[3] $ D1L486;

--D1L479 is module_9851:inst2|add~2027 at LC_X12_Y9_N4
--operation mode is arithmetic

D1L479 = D1L480;


--D1L482 is module_9851:inst2|add~2030 at LC_X12_Y9_N2
--operation mode is arithmetic

D1L482 = D1_Count2[1] $ D1L476;