ad9851_2007.fit.qmsg

计算实用教程adadad9851实用教程

{ "Info" "ITAN_TDC_USER_OPTIMIZATION_GOALS" "" "Info: Detected fmax, tsu, tco, and/or tpd requirements -- optimizing circuit to achieve only the specified requirements" {  } {  } 0 0 "Detected fmax, tsu, tco, and/or tpd requirements -- optimizing circuit to achieve only the specified requirements" 0 0}
{ "Info" "IFSAC_FSAC_START_REG_LOCATION_PROCESSING" "" "Info: Performing register packing on registers with non-logic cell location assignments" {  } {  } 0 0 "Performing register packing on registers with non-logic cell location assignments" 0 0}
{ "Info" "IFSAC_FSAC_FINISH_REG_LOCATION_PROCESSING" "" "Info: Completed register packing on registers with non-logic cell location assignments" {  } {  } 0 0 "Completed register packing on registers with non-logic cell location assignments" 0 0}
{ "Info" "IFYGR_FYGR_OPINFO_COMPLETED_OP" "User Assigned Global Signals Promotion Operation " "Info: Completed User Assigned Global Signals Promotion Operation" {  } {  } 0 0 "Completed %1!s!" 0 0}
{ "Info" "IFYGR_FYGR_GLOBAL_LINES_NEEDED_FOR_TORNADO_DQS" "0 " "Info: DQS I/O pins require 0 global routing resources" {  } {  } 0 0 "DQS I/O pins require %1!d! global routing resources" 0 0}
{ "Info" "IFYGR_FYGR_PLL_CLK_PROMOTION" "" "Info: Promoted PLL clock signals" { { "Info" "IFYGR_FYGR_PLL_PROMOTE_GCLK" "CLK " "Info: Promoted signal \"CLK\" to use global clock" {  } { { "e:/altera/quartus51/bin/Assignment Editor.qase" "" { Assignment "e:/altera/quartus51/bin/Assignment Editor.qase" 1 { { 0 "CLK" } { 0 "CLK" } } } } { "ad9851_2007.bdf" "" { Schematic "C:/Documents and Settings/Administrator/桌面/ad9851_2007/ad9851_2007.bdf" { { -240 -224 -56 -224 "CLK" "" } { 344 -360 -256 360 "CLK" "" } { 488 -344 -304 504 "CLK" "" } { 680 416 432 712 "CLK" "" } { 696 208 248 712 "CLK" "" } { -248 336 384 -232 "CLK" "" } } } } { "e:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "e:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "ad9851_2007" "UNKNOWN" "V1" "C:/Documents and Settings/Administrator/桌面/ad9851_2007/db/ad9851_2007.quartus_db" { Floorplan "C:/Documents and Settings/Administrator/桌面/ad9851_2007/" "" "" { CLK } "NODE_NAME" } "" } } { "C:/Documents and Settings/Administrator/桌面/ad9851_2007/ad9851_2007.fld" "" { Floorplan "C:/Documents and Settings/Administrator/桌面/ad9851_2007/ad9851_2007.fld" "" "" { CLK } "NODE_NAME" } }  } 0 0 "Promoted signal \"%1!s!\" to use global clock" 0 0} { "Info" "IFYGR_FYGR_PLL_PROMOTE_GCLK_USER" "altpll0:inst6\|altpll:altpll_component\|_clk0 " "Info: Promoted signal \"altpll0:inst6\|altpll:altpll_component\|_clk0\" to use global clock (user assigned)" {  } { { "e:/altera/quartus51/bin/Assignment Editor.qase" "" { Assignment "e:/altera/quartus51/bin/Assignment Editor.qase" 1 { { 0 "altpll0:inst6\|altpll:altpll_component\|_clk0" } { 0 "altpll0:inst6\|altpll:altpll_component\|_clk0" } } } } { "ad9851_2007.bdf" "" { Schematic "C:/Documents and Settings/Administrator/桌面/ad9851_2007/ad9851_2007.bdf" { { 440 -304 -64 600 "inst6" "" } } } } { "altpll.tdf" "" { Text "e:/altera/quartus51/libraries/megafunctions/altpll.tdf" 763 3 0 } } { "e:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "e:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "ad9851_2007" "UNKNOWN" "V1" "C:/Documents and Settings/Administrator/桌面/ad9851_2007/db/ad9851_2007.quartus_db" { Floorplan "C:/Documents and Settings/Administrator/桌面/ad9851_2007/" "" "" { altpll0:inst6|altpll:altpll_component|_clk0 } "NODE_NAME" } "" } } { "C:/Documents and Settings/Administrator/桌面/ad9851_2007/ad9851_2007.fld" "" { Floorplan "C:/Documents and Settings/Administrator/桌面/ad9851_2007/ad9851_2007.fld" "" "" { altpll0:inst6|altpll:altpll_component|_clk0 } "NODE_NAME" } }  } 0 0 "Promoted signal \"%1!s!\" to use global clock (user assigned)" 0 0}  } {  } 0 0 "Promoted PLL clock signals" 0 0}
{ "Info" "IFYGR_FYGR_OPINFO_COMPLETED_OP" "PLL Placement Operation " "Info: Completed PLL Placement Operation" {  } {  } 0 0 "Completed %1!s!" 0 0}
{ "Info" "IFYGR_FYGR_AUTO_GLOBAL_ASSIGNED_SOME_TO_GLOBAL" "fp_2:inst3\|Cout Global clock " "Info: Automatically promoted some destinations of signal \"fp_2:inst3\|Cout\" to use Global clock" { { "Info" "IFYGR_FYGR_AUTO_GLOBAL_ASSIGNED_SOME_TO_GLOBAL_SUB" "fp_2:inst3\|Cout " "Info: Destination \"fp_2:inst3\|Cout\" may be non-global or may not use global clock" {  } { { "fp_2.v" "" { Text "C:/Documents and Settings/Administrator/桌面/ad9851_2007/fp_2.v" 13 -1 0 } }  } 0 0 "Destination \"%1!s!\" may be non-global or may not use global clock" 0 0}  } { { "fp_2.v" "" { Text "C:/Documents and Settings/Administrator/桌面/ad9851_2007/fp_2.v" 13 -1 0 } }  } 0 0 "Automatically promoted some destinations of signal \"%1!s!\" to use %2!s!" 0 0}