ad9851_2007.map.qmsg

计算实用教程adadad9851实用教程

{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "a_csnbuffer lpm_mult0:inst15\|lpm_mult:lpm_mult_component\|multcore:mult_core\|mpar_add:padder\|lpm_add_sub:adder\[0\]\|addcore:adder\|a_csnbuffer:result_node " "Info: Elaborating entity \"a_csnbuffer\" for hierarchy \"lpm_mult0:inst15\|lpm_mult:lpm_mult_component\|multcore:mult_core\|mpar_add:padder\|lpm_add_sub:adder\[0\]\|addcore:adder\|a_csnbuffer:result_node\"" {  } { { "addcore.tdf" "result_node" { Text "e:/altera/quartus51/libraries/megafunctions/addcore.tdf" 120 6 0 } }  } 0 0 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0}
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "e:/altera/quartus51/libraries/megafunctions/altshift.tdf 1 1 " "Info: Found 1 design units, including 1 entities, in source file e:/altera/quartus51/libraries/megafunctions/altshift.tdf" { { "Info" "ISGN_ENTITY_NAME" "1 altshift " "Info: Found entity 1: altshift" {  } { { "altshift.tdf" "" { Text "e:/altera/quartus51/libraries/megafunctions/altshift.tdf" 28 1 0 } }  } 0 0 "Found entity %1!d!: %2!s!" 0 0}  } {  } 0 0 "Found %2!d! design units, including %3!d! entities, in source file %1!s!" 0 0}
{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "altshift lpm_mult0:inst15\|lpm_mult:lpm_mult_component\|multcore:mult_core\|mpar_add:padder\|lpm_add_sub:adder\[0\]\|altshift:result_ext_latency_ffs " "Info: Elaborating entity \"altshift\" for hierarchy \"lpm_mult0:inst15\|lpm_mult:lpm_mult_component\|multcore:mult_core\|mpar_add:padder\|lpm_add_sub:adder\[0\]\|altshift:result_ext_latency_ffs\"" {  } { { "lpm_add_sub.tdf" "result_ext_latency_ffs" { Text "e:/altera/quartus51/libraries/megafunctions/lpm_add_sub.tdf" 284 2 0 } }  } 0 0 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0}
{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "altshift lpm_mult0:inst15\|lpm_mult:lpm_mult_component\|multcore:mult_core\|mpar_add:padder\|lpm_add_sub:adder\[0\]\|altshift:carry_ext_latency_ffs " "Info: Elaborating entity \"altshift\" for hierarchy \"lpm_mult0:inst15\|lpm_mult:lpm_mult_component\|multcore:mult_core\|mpar_add:padder\|lpm_add_sub:adder\[0\]\|altshift:carry_ext_latency_ffs\"" {  } { { "lpm_add_sub.tdf" "carry_ext_latency_ffs" { Text "e:/altera/quartus51/libraries/megafunctions/lpm_add_sub.tdf" 286 2 0 } }  } 0 0 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0}
{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "altshift lpm_mult0:inst15\|lpm_mult:lpm_mult_component\|altshift:external_latency_ffs " "Info: Elaborating entity \"altshift\" for hierarchy \"lpm_mult0:inst15\|lpm_mult:lpm_mult_component\|altshift:external_latency_ffs\"" {  } { { "lpm_mult.tdf" "external_latency_ffs" { Text "e:/altera/quartus51/libraries/megafunctions/lpm_mult.tdf" 347 4 0 } }  } 0 0 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0}
{ "Warning" "WSGN_SEARCH_FILE" "lpm_rom0.v 1 1 " "Warning: Using design file lpm_rom0.v, which is not specified as a design file for the current project, but contains definitions for 1 design units and 1 entities in project" { { "Info" "ISGN_ENTITY_NAME" "1 lpm_rom0 " "Info: Found entity 1: lpm_rom0" {  } { { "lpm_rom0.v" "" { Text "C:/Documents and Settings/Administrator/桌面/ad9851_2007/lpm_rom0.v" 36 -1 0 } }  } 0 0 "Found entity %1!d!: %2!s!" 0 0}  } {  } 0 0 "Using design file %1!s!, which is not specified as a design file for the current project, but contains definitions for %2!d! design units and %3!d! entities in project" 0 0}
{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "lpm_rom0 lpm_rom0:inst11 " "Info: Elaborating entity \"lpm_rom0\" for hierarchy \"lpm_rom0:inst11\"" {  } { { "ad9851_2007.bdf" "inst11" { Schematic "C:/Documents and Settings/Administrator/桌面/ad9851_2007/ad9851_2007.bdf" { { 440 336 496 520 "inst11" "" } } } }  } 0 0 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0}
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "e:/altera/quartus51/libraries/megafunctions/altsyncram.tdf 1 1 " "Info: Found 1 design units, including 1 entities, in source file e:/altera/quartus51/libraries/megafunctions/altsyncram.tdf" { { "Info" "ISGN_ENTITY_NAME" "1 altsyncram " "Info: Found entity 1: altsyncram" {  } { { "altsyncram.tdf" "" { Text "e:/altera/quartus51/libraries/megafunctions/altsyncram.tdf" 425 1 0 } }  } 0 0 "Found entity %1!d!: %2!s!" 0 0}  } {  } 0 0 "Found %2!d! design units, including %3!d! entities, in source file %1!s!" 0 0}
{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "altsyncram lpm_rom0:inst11\|altsyncram:altsyncram_component " "Info: Elaborating entity \"altsyncram\" for hierarchy \"lpm_rom0:inst11\|altsyncram:altsyncram_component\"" {  } { { "lpm_rom0.v" "altsyncram_component" { Text "C:/Documents and Settings/Administrator/桌面/ad9851_2007/lpm_rom0.v" 48 -1 0 } }  } 0 0 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0}
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "db/altsyncram_n8s.tdf 1 1 " "Info: Found 1 design units, including 1 entities, in source file db/altsyncram_n8s.tdf" { { "Info" "ISGN_ENTITY_NAME" "1 altsyncram_n8s " "Info: Found entity 1: altsyncram_n8s" {  } { { "db/altsyncram_n8s.tdf" "" { Text "C:/Documents and Settings/Administrator/桌面/ad9851_2007/db/altsyncram_n8s.tdf" 36 1 0 } }  } 0 0 "Found entity %1!d!: %2!s!" 0 0}  } {  } 0 0 "Found %2!d! design units, including %3!d! entities, in source file %1!s!" 0 0}
{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "altsyncram_n8s lpm_rom0:inst11\|altsyncram:altsyncram_component\|altsyncram_n8s:auto_generated " "Info: Elaborating entity \"altsyncram_n8s\" for hierarchy \"lpm_rom0:inst11\|altsyncram:altsyncram_component\|altsyncram_n8s:auto_generated\"" {  } { { "altsyncram.tdf" "auto_generated" { Text "e:/altera/quartus51/libraries/megafunctions/altsyncram.tdf" 903 3 0 } }  } 0 0 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0}
{ "Warning" "WSGN_SEARCH_FILE" "ROM256ADDR.v 1 1 " "Warning: Using design file ROM256ADDR.v, which is not specified as a design file for the current project, but contains definitions for 1 design units and 1 entities in project" { { "Info" "ISGN_ENTITY_NAME" "1 ROM256ADDR " "Info: Found entity 1: ROM256ADDR" {  } { { "ROM256ADDR.v" "" { Text "C:/Documents and Settings/Administrator/桌面/ad9851_2007/ROM256ADDR.v" 1 -1 0 } }  } 0 0 "Found entity %1!d!: %2!s!" 0 0}  } {  } 0 0 "Using design file %1!s!, which is not specified as a design file for the current project, but contains definitions for %2!d! design units and %3!d! entities in project" 0 0}
{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "ROM256ADDR ROM256ADDR:inst10 " "Info: Elaborating entity \"ROM256ADDR\" for hierarchy \"ROM256ADDR:inst10\"" {  } { { "ad9851_2007.bdf" "inst10" { Schematic "C:/Documents and Settings/Administrator/桌面/ad9851_2007/ad9851_2007.bdf" { { 440 136 256 536 "inst10" "" } } } }  } 0 0 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0}
{ "Warning" "WVRFX_VERI_EXPRESSION_TRUNCATED_TO_FIT" "32 8 ROM256ADDR.v(13) " "Warning (10230): Verilog HDL assignment warning at ROM256ADDR.v(13): truncated value with size 32 to match size of target (8)" {  } { { "ROM256ADDR.v" "" { Text "C:/Documents and Settings/Administrator/桌面/ad9851_2007/ROM256ADDR.v" 13 0 0 } }  } 0 10230 "Verilog HDL assignment warning at %3!s!: truncated value with size %1!d! to match size of target (%2!d!)" 0 0}
{ "Warning" "WSGN_SEARCH_FILE" "fp_5.v 1 1 " "Warning: Using design file fp_5.v, which is not specified as a design file for the current project, but contains definitions for 1 design units and 1 entities in project" { { "Info" "ISGN_ENTITY_NAME" "1 fp_5 " "Info: Found entity 1: fp_5" {  } { { "fp_5.v" "" { Text "C:/Documents and Settings/Administrator/桌面/ad9851_2007/fp_5.v" 1 -1 0 } }  } 0 0 "Found entity %1!d!: %2!s!" 0 0}  } {  } 0 0 "Using design file %1!s!, which is not specified as a design file for the current project, but contains definitions for %2!d! design units and %3!d! entities in project" 0 0}
{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "fp_5 fp_5:inst9 " "Info: Elaborating entity \"fp_5\" for hierarchy \"fp_5:inst9\"" {  } { { "ad9851_2007.bdf" "inst9" { Schematic "C:/Documents and Settings/Administrator/桌面/ad9851_2007/ad9851_2007.bdf" { { 672 -48 80 768 "inst9" "" } } } }  } 0 0 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0}
{ "Warning" "WVRFX_VERI_EXPRESSION_TRUNCATED_TO_FIT" "32 3 fp_5.v(13) " "Warning (10230): Verilog HDL assignment warning at fp_5.v(13): truncated value with size 32 to match size of target (3)" {  } { { "fp_5.v" "" { Text "C:/Documents and Settings/Administrator/桌面/ad9851_2007/fp_5.v" 13 0 0 } }  } 0 10230 "Verilog HDL assignment warning at %3!s!: truncated value with size %1!d! to match size of target (%2!d!)" 0 0}
{ "Warning" "WSGN_SEARCH_FILE" "altpll0.v 1 1 " "Warning: Using design file altpll0.v, which is not specified as a design file for the current project, but contains definitions for 1 design units and 1 entities in project" { { "Info" "ISGN_ENTITY_NAME" "1 altpll0 " "Info: Found entity 1: altpll0" {  } { { "altpll0.v" "" { Text "C:/Documents and Settings/Administrator/桌面/ad9851_2007/altpll0.v" 36 -1 0 } }  } 0 0 "Found entity %1!d!: %2!s!" 0 0}  } {  } 0 0 "Using design file %1!s!, which is not specified as a design file for the current project, but contains definitions for %2!d! design units and %3!d! entities in project" 0 0}
{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "altpll0 altpll0:inst6 " "Info: Elaborating entity \"altpll0\" for hierarchy \"altpll0:inst6\"" {  } { { "ad9851_2007.bdf" "inst6" { Schematic "C:/Documents and Settings/Administrator/桌面/ad9851_2007/ad9851_2007.bdf" { { 440 -304 -64 600 "inst6" "" } } } }  } 0 0 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0}
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "e:/altera/quartus51/libraries/megafunctions/altpll.tdf 1 1 " "Info: Found 1 design units, including 1 entities, in source file e:/altera/quartus51/libraries/megafunctions/altpll.tdf" { { "Info" "ISGN_ENTITY_NAME" "1 altpll " "Info: Found entity 1: altpll" {  } { { "altpll.tdf" "" { Text "e:/altera/quartus51/libraries/megafunctions/altpll.tdf" 363 1 0 } }  } 0 0 "Found entity %1!d!: %2!s!" 0 0}  } {  } 0 0 "Found %2!d! design units, including %3!d! entities, in source file %1!s!" 0 0}
{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "altpll altpll0:inst6\|altpll:altpll_component " "Info: Elaborating entity \"altpll\" for hierarchy \"altpll0:inst6\|altpll:altpll_component\"" {  } { { "altpll0.v" "altpll_component" { Text "C:/Documents and Settings/Administrator/桌面/ad9851_2007/altpll0.v" 50 -1 0 } }  } 0 0 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0}
{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "dac0832 dac0832:inst20 " "Info: Elaborating entity \"dac0832\" for hierarchy \"dac0832:inst20\"" {  } { { "ad9851_2007.bdf" "inst20" { Schematic "C:/Documents and Settings/Administrator/桌面/ad9851_2007/ad9851_2007.bdf" { { 784 288 472 880 "inst20" "" } } } }  } 0 0 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0}
{ "Warning" "WVRFX_VERI_ALWAYS_ID_HOLDS_VALUE" "data_out dac0832.v(17) " "Warning (10240): Verilog HDL Always Construct warning at dac0832.v(17): variable \"data_out\" may not be assigned a new value in every possible path through the Always Construct.  Variable \"data_out\" holds its previous value in every path with no new value assignment, which may create a combinational loop in the current design." {  } { { "dac0832.v" "" { Text "C:/Documents and Settings/Administrator/桌面/ad9851_2007/dac0832.v" 17 0 0 } }  } 0 10240 "Verilog HDL Always Construct warning at %2!s!: variable \"%1!s!\" may not be assigned a new value in every possible path through the Always Construct.  Variable \"%1!s!\" holds its previous value in every path with no new value assignment, which may create a combinational loop in the current design." 0 0}
{ "Warning" "WSGN_SEARCH_FILE" "ScanKey.v 1 1 " "Warning: Using design file ScanKey.v, which is not specified as a design file for the current project, but contains definitions for 1 design units and 1 entities in project" { { "Info" "ISGN_ENTITY_NAME" "1 ScanKey " "Info: Found entity 1: ScanKey" {  } { { "ScanKey.v" "" { Text "C:/Documents and Settings/Administrator/桌面/ad9851_2007/ScanKey.v" 1 -1 0 } }  } 0 0 "Found entity %1!d!: %2!s!" 0 0}  } {  } 0 0 "Using design file %1!s!, which is not specified as a design file for the current project, but contains definitions for %2!d! design units and %3!d! entities in project" 0 0}
{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "ScanKey ScanKey:inst29 " "Info: Elaborating entity \"ScanKey\" for hierarchy \"ScanKey:inst29\"" {  } { { "ad9851_2007.bdf" "inst29" { Schematic "C:/Documents and Settings/Administrator/桌面/ad9851_2007/ad9851_2007.bdf" { { -832 104 248 -704 "inst29" "" } } } }  } 0 0 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0}
{ "Info" "IVRFX_VRFC_OBJECT_DECLARED_NOT_USED" "CS ScanKey.v(4) " "Info (10035): Verilog HDL or VHDL information at ScanKey.v(4): object \"CS\" declared but not used" {  } { { "ScanKey.v" "" { Text "C:/Documents and Settings/Administrator/桌面/ad9851_2007/ScanKey.v" 4 0 0 } }  } 0 10035 "Verilog HDL or VHDL information at %2!s!: object \"%1!s!\" declared but not used" 0 0}
{ "Info" "IVRFX_VRFC_OBJECT_DECLARED_NOT_USED" "RD ScanKey.v(5) " "Info (10035): Verilog HDL or VHDL information at ScanKey.v(5): object \"RD\" declared but not used" {  } { { "ScanKey.v" "" { Text "C:/Documents and Settings/Administrator/桌面/ad9851_2007/ScanKey.v" 5 0 0 } }  } 0 10035 "Verilog HDL or VHDL information at %2!s!: object \"%1!s!\" declared but not used" 0 0}
{ "Warning" "WVRFX_VERI_EXPRESSION_TRUNCATED_TO_FIT" "32 1 ScanKey.v(24) " "Warning (10230): Verilog HDL assignment warning at ScanKey.v(24): truncated value with size 32 to match size of target (1)" {  } { { "ScanKey.v" "" { Text "C:/Documents and Settings/Administrator/桌面/ad9851_2007/ScanKey.v" 24 0 0 } }  } 0 10230 "Verilog HDL assignment warning at %3!s!: truncated value with size %1!d! to match size of target (%2!d!)" 0 0}