ad9851_2007.map.qmsg

计算实用教程adadad9851实用教程

{ "Warning" "WVRFX_VERI_EXPRESSION_TRUNCATED_TO_FIT" "32 3 PSK_ASK.v(22) " "Warning (10230): Verilog HDL assignment warning at PSK_ASK.v(22): truncated value with size 32 to match size of target (3)" {  } { { "PSK_ASK.v" "" { Text "C:/Documents and Settings/Administrator/桌面/ad9851_2007/PSK_ASK.v" 22 0 0 } }  } 0 10230 "Verilog HDL assignment warning at %3!s!: truncated value with size %1!d! to match size of target (%2!d!)" 0 0}
{ "Warning" "WVRFX_VERI_CASE_ITEM_EXPR_TOO_LARGE" "32 3 PSK_ASK.v(28) " "Warning (10271): Verilog HDL Case Statement warning at PSK_ASK.v(28): size of case item expression (32) exceeds the size of the case expression (3)" {  } { { "PSK_ASK.v" "" { Text "C:/Documents and Settings/Administrator/桌面/ad9851_2007/PSK_ASK.v" 28 0 0 } }  } 0 10271 "Verilog HDL Case Statement warning at %3!s!: size of case item expression (%1!d!) exceeds the size of the case expression (%2!d!)" 0 0}
{ "Warning" "WVRFX_VERI_CASE_ITEM_EXPR_TOO_LARGE" "32 3 PSK_ASK.v(29) " "Warning (10271): Verilog HDL Case Statement warning at PSK_ASK.v(29): size of case item expression (32) exceeds the size of the case expression (3)" {  } { { "PSK_ASK.v" "" { Text "C:/Documents and Settings/Administrator/桌面/ad9851_2007/PSK_ASK.v" 29 0 0 } }  } 0 10271 "Verilog HDL Case Statement warning at %3!s!: size of case item expression (%1!d!) exceeds the size of the case expression (%2!d!)" 0 0}
{ "Warning" "WVRFX_VERI_CASE_ITEM_EXPR_TOO_LARGE" "32 3 PSK_ASK.v(30) " "Warning (10271): Verilog HDL Case Statement warning at PSK_ASK.v(30): size of case item expression (32) exceeds the size of the case expression (3)" {  } { { "PSK_ASK.v" "" { Text "C:/Documents and Settings/Administrator/桌面/ad9851_2007/PSK_ASK.v" 30 0 0 } }  } 0 10271 "Verilog HDL Case Statement warning at %3!s!: size of case item expression (%1!d!) exceeds the size of the case expression (%2!d!)" 0 0}
{ "Warning" "WVRFX_VERI_CASE_ITEM_EXPR_TOO_LARGE" "32 3 PSK_ASK.v(31) " "Warning (10271): Verilog HDL Case Statement warning at PSK_ASK.v(31): size of case item expression (32) exceeds the size of the case expression (3)" {  } { { "PSK_ASK.v" "" { Text "C:/Documents and Settings/Administrator/桌面/ad9851_2007/PSK_ASK.v" 31 0 0 } }  } 0 10271 "Verilog HDL Case Statement warning at %3!s!: size of case item expression (%1!d!) exceeds the size of the case expression (%2!d!)" 0 0}
{ "Warning" "WVRFX_VERI_CASE_ITEM_EXPR_TOO_LARGE" "32 3 PSK_ASK.v(32) " "Warning (10271): Verilog HDL Case Statement warning at PSK_ASK.v(32): size of case item expression (32) exceeds the size of the case expression (3)" {  } { { "PSK_ASK.v" "" { Text "C:/Documents and Settings/Administrator/桌面/ad9851_2007/PSK_ASK.v" 32 0 0 } }  } 0 10271 "Verilog HDL Case Statement warning at %3!s!: size of case item expression (%1!d!) exceeds the size of the case expression (%2!d!)" 0 0}
{ "Warning" "WVRFX_VERI_CASE_ITEM_EXPR_TOO_LARGE" "32 3 PSK_ASK.v(33) " "Warning (10271): Verilog HDL Case Statement warning at PSK_ASK.v(33): size of case item expression (32) exceeds the size of the case expression (3)" {  } { { "PSK_ASK.v" "" { Text "C:/Documents and Settings/Administrator/桌面/ad9851_2007/PSK_ASK.v" 33 0 0 } }  } 0 10271 "Verilog HDL Case Statement warning at %3!s!: size of case item expression (%1!d!) exceeds the size of the case expression (%2!d!)" 0 0}
{ "Warning" "WVRFX_VERI_CASE_ITEM_EXPR_TOO_LARGE" "32 3 PSK_ASK.v(34) " "Warning (10271): Verilog HDL Case Statement warning at PSK_ASK.v(34): size of case item expression (32) exceeds the size of the case expression (3)" {  } { { "PSK_ASK.v" "" { Text "C:/Documents and Settings/Administrator/桌面/ad9851_2007/PSK_ASK.v" 34 0 0 } }  } 0 10271 "Verilog HDL Case Statement warning at %3!s!: size of case item expression (%1!d!) exceeds the size of the case expression (%2!d!)" 0 0}
{ "Warning" "WVRFX_VERI_CASE_ITEM_EXPR_TOO_LARGE" "32 3 PSK_ASK.v(35) " "Warning (10271): Verilog HDL Case Statement warning at PSK_ASK.v(35): size of case item expression (32) exceeds the size of the case expression (3)" {  } { { "PSK_ASK.v" "" { Text "C:/Documents and Settings/Administrator/桌面/ad9851_2007/PSK_ASK.v" 35 0 0 } }  } 0 10271 "Verilog HDL Case Statement warning at %3!s!: size of case item expression (%1!d!) exceeds the size of the case expression (%2!d!)" 0 0}
{ "Warning" "WSGN_SEARCH_FILE" "fp_10.v 1 1 " "Warning: Using design file fp_10.v, which is not specified as a design file for the current project, but contains definitions for 1 design units and 1 entities in project" { { "Info" "ISGN_ENTITY_NAME" "1 fp_10 " "Info: Found entity 1: fp_10" {  } { { "fp_10.v" "" { Text "C:/Documents and Settings/Administrator/桌面/ad9851_2007/fp_10.v" 1 -1 0 } }  } 0 0 "Found entity %1!d!: %2!s!" 0 0}  } {  } 0 0 "Using design file %1!s!, which is not specified as a design file for the current project, but contains definitions for %2!d! design units and %3!d! entities in project" 0 0}
{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "fp_10 fp_10:inst19 " "Info: Elaborating entity \"fp_10\" for hierarchy \"fp_10:inst19\"" {  } { { "ad9851_2007.bdf" "inst19" { Schematic "C:/Documents and Settings/Administrator/桌面/ad9851_2007/ad9851_2007.bdf" { { 792 -16 80 888 "inst19" "" } } } }  } 0 0 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0}
{ "Warning" "WVRFX_VERI_EXPRESSION_TRUNCATED_TO_FIT" "32 4 fp_10.v(18) " "Warning (10230): Verilog HDL assignment warning at fp_10.v(18): truncated value with size 32 to match size of target (4)" {  } { { "fp_10.v" "" { Text "C:/Documents and Settings/Administrator/桌面/ad9851_2007/fp_10.v" 18 0 0 } }  } 0 10230 "Verilog HDL assignment warning at %3!s!: truncated value with size %1!d! to match size of target (%2!d!)" 0 0}
{ "Warning" "WSGN_SEARCH_FILE" "ASIC74573.v 1 1 " "Warning: Using design file ASIC74573.v, which is not specified as a design file for the current project, but contains definitions for 1 design units and 1 entities in project" { { "Info" "ISGN_ENTITY_NAME" "1 ASIC74573 " "Info: Found entity 1: ASIC74573" {  } { { "ASIC74573.v" "" { Text "C:/Documents and Settings/Administrator/桌面/ad9851_2007/ASIC74573.v" 1 -1 0 } }  } 0 0 "Found entity %1!d!: %2!s!" 0 0}  } {  } 0 0 "Using design file %1!s!, which is not specified as a design file for the current project, but contains definitions for %2!d! design units and %3!d! entities in project" 0 0}
{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "ASIC74573 ASIC74573:inst4 " "Info: Elaborating entity \"ASIC74573\" for hierarchy \"ASIC74573:inst4\"" {  } { { "ad9851_2007.bdf" "inst4" { Schematic "C:/Documents and Settings/Administrator/桌面/ad9851_2007/ad9851_2007.bdf" { { -176 184 328 -80 "inst4" "" } } } }  } 0 0 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0}
{ "Warning" "WSGN_SEARCH_FILE" "lpm_mult0.v 1 1 " "Warning: Using design file lpm_mult0.v, which is not specified as a design file for the current project, but contains definitions for 1 design units and 1 entities in project" { { "Info" "ISGN_ENTITY_NAME" "1 lpm_mult0 " "Info: Found entity 1: lpm_mult0" {  } { { "lpm_mult0.v" "" { Text "C:/Documents and Settings/Administrator/桌面/ad9851_2007/lpm_mult0.v" 36 -1 0 } }  } 0 0 "Found entity %1!d!: %2!s!" 0 0}  } {  } 0 0 "Using design file %1!s!, which is not specified as a design file for the current project, but contains definitions for %2!d! design units and %3!d! entities in project" 0 0}
{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "lpm_mult0 lpm_mult0:inst15 " "Info: Elaborating entity \"lpm_mult0\" for hierarchy \"lpm_mult0:inst15\"" {  } { { "ad9851_2007.bdf" "inst15" { Schematic "C:/Documents and Settings/Administrator/桌面/ad9851_2007/ad9851_2007.bdf" { { 440 552 720 536 "inst15" "" } } } }  } 0 0 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0}
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "e:/altera/quartus51/libraries/megafunctions/lpm_mult.tdf 1 1 " "Info: Found 1 design units, including 1 entities, in source file e:/altera/quartus51/libraries/megafunctions/lpm_mult.tdf" { { "Info" "ISGN_ENTITY_NAME" "1 lpm_mult " "Info: Found entity 1: lpm_mult" {  } { { "lpm_mult.tdf" "" { Text "e:/altera/quartus51/libraries/megafunctions/lpm_mult.tdf" 281 1 0 } }  } 0 0 "Found entity %1!d!: %2!s!" 0 0}  } {  } 0 0 "Found %2!d! design units, including %3!d! entities, in source file %1!s!" 0 0}
{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "lpm_mult lpm_mult0:inst15\|lpm_mult:lpm_mult_component " "Info: Elaborating entity \"lpm_mult\" for hierarchy \"lpm_mult0:inst15\|lpm_mult:lpm_mult_component\"" {  } { { "lpm_mult0.v" "lpm_mult_component" { Text "C:/Documents and Settings/Administrator/桌面/ad9851_2007/lpm_mult0.v" 47 -1 0 } }  } 0 0 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0}
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "e:/altera/quartus51/libraries/megafunctions/multcore.tdf 1 1 " "Info: Found 1 design units, including 1 entities, in source file e:/altera/quartus51/libraries/megafunctions/multcore.tdf" { { "Info" "ISGN_ENTITY_NAME" "1 multcore " "Info: Found entity 1: multcore" {  } { { "multcore.tdf" "" { Text "e:/altera/quartus51/libraries/megafunctions/multcore.tdf" 175 1 0 } }  } 0 0 "Found entity %1!d!: %2!s!" 0 0}  } {  } 0 0 "Found %2!d! design units, including %3!d! entities, in source file %1!s!" 0 0}
{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "multcore lpm_mult0:inst15\|lpm_mult:lpm_mult_component\|multcore:mult_core " "Info: Elaborating entity \"multcore\" for hierarchy \"lpm_mult0:inst15\|lpm_mult:lpm_mult_component\|multcore:mult_core\"" {  } { { "lpm_mult.tdf" "mult_core" { Text "e:/altera/quartus51/libraries/megafunctions/lpm_mult.tdf" 304 5 0 } }  } 0 0 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0}
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "e:/altera/quartus51/libraries/megafunctions/mpar_add.tdf 1 1 " "Info: Found 1 design units, including 1 entities, in source file e:/altera/quartus51/libraries/megafunctions/mpar_add.tdf" { { "Info" "ISGN_ENTITY_NAME" "1 mpar_add " "Info: Found entity 1: mpar_add" {  } { { "mpar_add.tdf" "" { Text "e:/altera/quartus51/libraries/megafunctions/mpar_add.tdf" 60 1 0 } }  } 0 0 "Found entity %1!d!: %2!s!" 0 0}  } {  } 0 0 "Found %2!d! design units, including %3!d! entities, in source file %1!s!" 0 0}
{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "mpar_add lpm_mult0:inst15\|lpm_mult:lpm_mult_component\|multcore:mult_core\|mpar_add:padder " "Info: Elaborating entity \"mpar_add\" for hierarchy \"lpm_mult0:inst15\|lpm_mult:lpm_mult_component\|multcore:mult_core\|mpar_add:padder\"" {  } { { "multcore.tdf" "padder" { Text "e:/altera/quartus51/libraries/megafunctions/multcore.tdf" 227 7 0 } }  } 0 0 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0}
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "e:/altera/quartus51/libraries/megafunctions/lpm_add_sub.tdf 1 1 " "Info: Found 1 design units, including 1 entities, in source file e:/altera/quartus51/libraries/megafunctions/lpm_add_sub.tdf" { { "Info" "ISGN_ENTITY_NAME" "1 lpm_add_sub " "Info: Found entity 1: lpm_add_sub" {  } { { "lpm_add_sub.tdf" "" { Text "e:/altera/quartus51/libraries/megafunctions/lpm_add_sub.tdf" 100 1 0 } }  } 0 0 "Found entity %1!d!: %2!s!" 0 0}  } {  } 0 0 "Found %2!d! design units, including %3!d! entities, in source file %1!s!" 0 0}
{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "lpm_add_sub lpm_mult0:inst15\|lpm_mult:lpm_mult_component\|multcore:mult_core\|mpar_add:padder\|lpm_add_sub:adder\[0\] " "Info: Elaborating entity \"lpm_add_sub\" for hierarchy \"lpm_mult0:inst15\|lpm_mult:lpm_mult_component\|multcore:mult_core\|mpar_add:padder\|lpm_add_sub:adder\[0\]\"" {  } { { "mpar_add.tdf" "adder\[0\]" { Text "e:/altera/quartus51/libraries/megafunctions/mpar_add.tdf" 78 8 0 } }  } 0 0 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0}
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "e:/altera/quartus51/libraries/megafunctions/addcore.tdf 1 1 " "Info: Found 1 design units, including 1 entities, in source file e:/altera/quartus51/libraries/megafunctions/addcore.tdf" { { "Info" "ISGN_ENTITY_NAME" "1 addcore " "Info: Found entity 1: addcore" {  } { { "addcore.tdf" "" { Text "e:/altera/quartus51/libraries/megafunctions/addcore.tdf" 73 1 0 } }  } 0 0 "Found entity %1!d!: %2!s!" 0 0}  } {  } 0 0 "Found %2!d! design units, including %3!d! entities, in source file %1!s!" 0 0}
{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "addcore lpm_mult0:inst15\|lpm_mult:lpm_mult_component\|multcore:mult_core\|mpar_add:padder\|lpm_add_sub:adder\[0\]\|addcore:adder " "Info: Elaborating entity \"addcore\" for hierarchy \"lpm_mult0:inst15\|lpm_mult:lpm_mult_component\|multcore:mult_core\|mpar_add:padder\|lpm_add_sub:adder\[0\]\|addcore:adder\"" {  } { { "lpm_add_sub.tdf" "adder" { Text "e:/altera/quartus51/libraries/megafunctions/lpm_add_sub.tdf" 266 4 0 } }  } 0 0 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0}
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "e:/altera/quartus51/libraries/megafunctions/a_csnbuffer.tdf 1 1 " "Info: Found 1 design units, including 1 entities, in source file e:/altera/quartus51/libraries/megafunctions/a_csnbuffer.tdf" { { "Info" "ISGN_ENTITY_NAME" "1 a_csnbuffer " "Info: Found entity 1: a_csnbuffer" {  } { { "a_csnbuffer.tdf" "" { Text "e:/altera/quartus51/libraries/megafunctions/a_csnbuffer.tdf" 10 1 0 } }  } 0 0 "Found entity %1!d!: %2!s!" 0 0}  } {  } 0 0 "Found %2!d! design units, including %3!d! entities, in source file %1!s!" 0 0}
{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "a_csnbuffer lpm_mult0:inst15\|lpm_mult:lpm_mult_component\|multcore:mult_core\|mpar_add:padder\|lpm_add_sub:adder\[0\]\|addcore:adder\|a_csnbuffer:oflow_node " "Info: Elaborating entity \"a_csnbuffer\" for hierarchy \"lpm_mult0:inst15\|lpm_mult:lpm_mult_component\|multcore:mult_core\|mpar_add:padder\|lpm_add_sub:adder\[0\]\|addcore:adder\|a_csnbuffer:oflow_node\"" {  } { { "addcore.tdf" "oflow_node" { Text "e:/altera/quartus51/libraries/megafunctions/addcore.tdf" 94 2 0 } }  } 0 0 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0}