ad9851_2007.map.qmsg

计算实用教程adadad9851实用教程

{ "Info" "IQEXE_SEPARATOR" "" "Info: *******************************************************************" {  } {  } 3 0 "*******************************************************************" 0 0}
{ "Info" "IQEXE_START_BANNER_PRODUCT" "Analysis & Synthesis Quartus II " "Info: Running Quartus II Analysis & Synthesis" { { "Info" "IQEXE_START_BANNER_VERSION" "Version 5.1 Build 176 10/26/2005 SJ Full Version " "Info: Version 5.1 Build 176 10/26/2005 SJ Full Version" {  } {  } 0 0 "%1!s!" 0 0} { "Info" "IQEXE_START_BANNER_TIME" "Tue Jan 01 10:03:20 2002 " "Info: Processing started: Tue Jan 01 10:03:20 2002" {  } {  } 0 0 "Processing started: %1!s!" 0 0}  } {  } 4 0 "Running %2!s! %1!s!" 0 0}
{ "Info" "IQEXE_START_BANNER_COMMANDLINE" "quartus_map --read_settings_files=on --write_settings_files=off ad9851_2007 -c ad9851_2007 " "Info: Command: quartus_map --read_settings_files=on --write_settings_files=off ad9851_2007 -c ad9851_2007" {  } {  } 0 0 "Command: %1!s!" 0 0}
{ "Warning" "WVRFX_VERI_LITERAL_TRUNCATED_TO_FIT" "7 module_9851.v(338) " "Warning (10229): Verilog HDL Expression warning at module_9851.v(338): truncated literal to match 7 bits" {  } { { "module_9851.v" "" { Text "C:/Documents and Settings/Administrator/桌面/ad9851_2007/module_9851.v" 338 0 0 } }  } 0 10229 "Verilog HDL Expression warning at %2!s!: truncated literal to match %1!d! bits" 0 0}
{ "Warning" "WVRFX_VERI_MIXED_BLOCKING_NONBLOCKING_ASSIGNMENT" "module_9851.v(46) " "Warning (10268): Verilog HDL information at module_9851.v(46): Always Construct contains both blocking and non-blocking assignments" {  } { { "module_9851.v" "" { Text "C:/Documents and Settings/Administrator/桌面/ad9851_2007/module_9851.v" 46 0 0 } }  } 0 10268 "Verilog HDL information at %1!s!: Always Construct contains both blocking and non-blocking assignments" 0 0}
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "module_9851.v 1 1 " "Info: Found 1 design units, including 1 entities, in source file module_9851.v" { { "Info" "ISGN_ENTITY_NAME" "1 module_9851 " "Info: Found entity 1: module_9851" {  } { { "module_9851.v" "" { Text "C:/Documents and Settings/Administrator/桌面/ad9851_2007/module_9851.v" 1 -1 0 } }  } 0 0 "Found entity %1!d!: %2!s!" 0 0}  } {  } 0 0 "Found %2!d! design units, including %3!d! entities, in source file %1!s!" 0 0}
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "ad9851_2007.bdf 1 1 " "Info: Found 1 design units, including 1 entities, in source file ad9851_2007.bdf" { { "Info" "ISGN_ENTITY_NAME" "1 ad9851_2007 " "Info: Found entity 1: ad9851_2007" {  } { { "ad9851_2007.bdf" "" { Schematic "C:/Documents and Settings/Administrator/桌面/ad9851_2007/ad9851_2007.bdf" { } } }  } 0 0 "Found entity %1!d!: %2!s!" 0 0}  } {  } 0 0 "Found %2!d! design units, including %3!d! entities, in source file %1!s!" 0 0}
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "dac0832.v 1 1 " "Info: Found 1 design units, including 1 entities, in source file dac0832.v" { { "Info" "ISGN_ENTITY_NAME" "1 dac0832 " "Info: Found entity 1: dac0832" {  } { { "dac0832.v" "" { Text "C:/Documents and Settings/Administrator/桌面/ad9851_2007/dac0832.v" 1 -1 0 } }  } 0 0 "Found entity %1!d!: %2!s!" 0 0}  } {  } 0 0 "Found %2!d! design units, including %3!d! entities, in source file %1!s!" 0 0}
{ "Info" "ISGN_START_ELABORATION_TOP" "ad9851_2007 " "Info: Elaborating entity \"ad9851_2007\" for the top level hierarchy" {  } {  } 0 0 "Elaborating entity \"%1!s!\" for the top level hierarchy" 0 0}
{ "Warning" "WGDFX_NO_SOURCE_FOR_PORT" "Din3 BUS_Connect inst24 " "Warning: Port \"Din3\" of type BUS_Connect and instance \"inst24\" is missing source signal" {  } { { "ad9851_2007.bdf" "" { Schematic "C:/Documents and Settings/Administrator/桌面/ad9851_2007/ad9851_2007.bdf" { { -568 96 248 -248 "inst24" "" } } } }  } 0 0 "Port \"%1!s!\" of type %2!s! and instance \"%3!s!\" is missing source signal" 0 0}
{ "Warning" "WGDFX_NO_SOURCE_FOR_PORT" "Din4 BUS_Connect inst24 " "Warning: Port \"Din4\" of type BUS_Connect and instance \"inst24\" is missing source signal" {  } { { "ad9851_2007.bdf" "" { Schematic "C:/Documents and Settings/Administrator/桌面/ad9851_2007/ad9851_2007.bdf" { { -568 96 248 -248 "inst24" "" } } } }  } 0 0 "Port \"%1!s!\" of type %2!s! and instance \"%3!s!\" is missing source signal" 0 0}
{ "Warning" "WGDFX_NO_SOURCE_FOR_PORT" "Din5 BUS_Connect inst24 " "Warning: Port \"Din5\" of type BUS_Connect and instance \"inst24\" is missing source signal" {  } { { "ad9851_2007.bdf" "" { Schematic "C:/Documents and Settings/Administrator/桌面/ad9851_2007/ad9851_2007.bdf" { { -568 96 248 -248 "inst24" "" } } } }  } 0 0 "Port \"%1!s!\" of type %2!s! and instance \"%3!s!\" is missing source signal" 0 0}
{ "Warning" "WGDFX_NO_SOURCE_FOR_PORT" "Din6 BUS_Connect inst24 " "Warning: Port \"Din6\" of type BUS_Connect and instance \"inst24\" is missing source signal" {  } { { "ad9851_2007.bdf" "" { Schematic "C:/Documents and Settings/Administrator/桌面/ad9851_2007/ad9851_2007.bdf" { { -568 96 248 -248 "inst24" "" } } } }  } 0 0 "Port \"%1!s!\" of type %2!s! and instance \"%3!s!\" is missing source signal" 0 0}
{ "Warning" "WGDFX_NO_SOURCE_FOR_PORT" "Din7 BUS_Connect inst24 " "Warning: Port \"Din7\" of type BUS_Connect and instance \"inst24\" is missing source signal" {  } { { "ad9851_2007.bdf" "" { Schematic "C:/Documents and Settings/Administrator/桌面/ad9851_2007/ad9851_2007.bdf" { { -568 96 248 -248 "inst24" "" } } } }  } 0 0 "Port \"%1!s!\" of type %2!s! and instance \"%3!s!\" is missing source signal" 0 0}
{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "module_9851 module_9851:inst2 " "Info: Elaborating entity \"module_9851\" for hierarchy \"module_9851:inst2\"" {  } { { "ad9851_2007.bdf" "inst2" { Schematic "C:/Documents and Settings/Administrator/桌面/ad9851_2007/ad9851_2007.bdf" { { 64 168 320 256 "inst2" "" } } } }  } 0 0 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0}
{ "Warning" "WVRFX_VERI_EXPRESSION_TRUNCATED_TO_FIT" "32 1 module_9851.v(45) " "Warning (10230): Verilog HDL assignment warning at module_9851.v(45): truncated value with size 32 to match size of target (1)" {  } { { "module_9851.v" "" { Text "C:/Documents and Settings/Administrator/桌面/ad9851_2007/module_9851.v" 45 0 0 } }  } 0 10230 "Verilog HDL assignment warning at %3!s!: truncated value with size %1!d! to match size of target (%2!d!)" 0 0}
{ "Warning" "WVRFX_VERI_INCOMPLETE_CASE_STATEMENT" "module_9851.v(50) " "Warning (10270): Verilog HDL statement warning at module_9851.v(50): incomplete Case Statement has no default case item" {  } { { "module_9851.v" "" { Text "C:/Documents and Settings/Administrator/桌面/ad9851_2007/module_9851.v" 50 0 0 } }  } 0 10270 "Verilog HDL statement warning at %1!s!: incomplete Case Statement has no default case item" 0 0}
{ "Warning" "WVRFX_VERI_INCOMPLETE_CASE_STATEMENT" "module_9851.v(71) " "Warning (10270): Verilog HDL statement warning at module_9851.v(71): incomplete Case Statement has no default case item" {  } { { "module_9851.v" "" { Text "C:/Documents and Settings/Administrator/桌面/ad9851_2007/module_9851.v" 71 0 0 } }  } 0 10270 "Verilog HDL statement warning at %1!s!: incomplete Case Statement has no default case item" 0 0}
{ "Warning" "WVRFX_VERI_INCOMPLETE_CASE_STATEMENT" "module_9851.v(160) " "Warning (10270): Verilog HDL statement warning at module_9851.v(160): incomplete Case Statement has no default case item" {  } { { "module_9851.v" "" { Text "C:/Documents and Settings/Administrator/桌面/ad9851_2007/module_9851.v" 160 0 0 } }  } 0 10270 "Verilog HDL statement warning at %1!s!: incomplete Case Statement has no default case item" 0 0}
{ "Warning" "WVRFX_VERI_INCOMPLETE_CASE_STATEMENT" "module_9851.v(250) " "Warning (10270): Verilog HDL statement warning at module_9851.v(250): incomplete Case Statement has no default case item" {  } { { "module_9851.v" "" { Text "C:/Documents and Settings/Administrator/桌面/ad9851_2007/module_9851.v" 250 0 0 } }  } 0 10270 "Verilog HDL statement warning at %1!s!: incomplete Case Statement has no default case item" 0 0}
{ "Warning" "WSGN_SEARCH_FILE" "fp_2.v 1 1 " "Warning: Using design file fp_2.v, which is not specified as a design file for the current project, but contains definitions for 1 design units and 1 entities in project" { { "Info" "ISGN_ENTITY_NAME" "1 fp_2 " "Info: Found entity 1: fp_2" {  } { { "fp_2.v" "" { Text "C:/Documents and Settings/Administrator/桌面/ad9851_2007/fp_2.v" 1 -1 0 } }  } 0 0 "Found entity %1!d!: %2!s!" 0 0}  } {  } 0 0 "Using design file %1!s!, which is not specified as a design file for the current project, but contains definitions for %2!d! design units and %3!d! entities in project" 0 0}
{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "fp_2 fp_2:inst3 " "Info: Elaborating entity \"fp_2\" for hierarchy \"fp_2:inst3\"" {  } { { "ad9851_2007.bdf" "inst3" { Schematic "C:/Documents and Settings/Administrator/桌面/ad9851_2007/ad9851_2007.bdf" { { 328 -96 0 424 "inst3" "" } } } }  } 0 0 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0}
{ "Warning" "WVRFX_VERI_EXPRESSION_TRUNCATED_TO_FIT" "32 1 fp_2.v(12) " "Warning (10230): Verilog HDL assignment warning at fp_2.v(12): truncated value with size 32 to match size of target (1)" {  } { { "fp_2.v" "" { Text "C:/Documents and Settings/Administrator/桌面/ad9851_2007/fp_2.v" 12 0 0 } }  } 0 10230 "Verilog HDL assignment warning at %3!s!: truncated value with size %1!d! to match size of target (%2!d!)" 0 0}
{ "Warning" "WSGN_SEARCH_FILE" "ASIC74138.v 1 1 " "Warning: Using design file ASIC74138.v, which is not specified as a design file for the current project, but contains definitions for 1 design units and 1 entities in project" { { "Info" "ISGN_ENTITY_NAME" "1 ASIC74138 " "Info: Found entity 1: ASIC74138" {  } { { "ASIC74138.v" "" { Text "C:/Documents and Settings/Administrator/桌面/ad9851_2007/ASIC74138.v" 1 -1 0 } }  } 0 0 "Found entity %1!d!: %2!s!" 0 0}  } {  } 0 0 "Using design file %1!s!, which is not specified as a design file for the current project, but contains definitions for %2!d! design units and %3!d! entities in project" 0 0}
{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "ASIC74138 ASIC74138:inst1 " "Info: Elaborating entity \"ASIC74138\" for hierarchy \"ASIC74138:inst1\"" {  } { { "ad9851_2007.bdf" "inst1" { Schematic "C:/Documents and Settings/Administrator/桌面/ad9851_2007/ad9851_2007.bdf" { { -56 176 336 40 "inst1" "" } } } }  } 0 0 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0}
{ "Warning" "WSGN_SEARCH_FILE" "PSK_ASK.v 1 1 " "Warning: Using design file PSK_ASK.v, which is not specified as a design file for the current project, but contains definitions for 1 design units and 1 entities in project" { { "Info" "ISGN_ENTITY_NAME" "1 PSK_ASK " "Info: Found entity 1: PSK_ASK" {  } { { "PSK_ASK.v" "" { Text "C:/Documents and Settings/Administrator/桌面/ad9851_2007/PSK_ASK.v" 1 -1 0 } }  } 0 0 "Found entity %1!d!: %2!s!" 0 0}  } {  } 0 0 "Using design file %1!s!, which is not specified as a design file for the current project, but contains definitions for %2!d! design units and %3!d! entities in project" 0 0}
{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "PSK_ASK PSK_ASK:inst12 " "Info: Elaborating entity \"PSK_ASK\" for hierarchy \"PSK_ASK:inst12\"" {  } { { "ad9851_2007.bdf" "inst12" { Schematic "C:/Documents and Settings/Administrator/桌面/ad9851_2007/ad9851_2007.bdf" { { 320 152 288 416 "inst12" "" } } } }  } 0 0 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0}
{ "Info" "IVRFX_VRFC_OBJECT_DECLARED_NOT_USED" "AD7501A0 PSK_ASK.v(16) " "Info (10035): Verilog HDL or VHDL information at PSK_ASK.v(16): object \"AD7501A0\" declared but not used" {  } { { "PSK_ASK.v" "" { Text "C:/Documents and Settings/Administrator/桌面/ad9851_2007/PSK_ASK.v" 16 0 0 } }  } 0 10035 "Verilog HDL or VHDL information at %2!s!: object \"%1!s!\" declared but not used" 0 0}