ad9851_2007.hier_info

计算实用教程adadad9851实用教程

CLK => KR_temp[1].CLK
CLK => KR_temp[0].CLK
CLK => Key_temp[4].CLK
CLK => Key_temp[3].CLK
CLK => Key_temp[2].CLK
CLK => Key_temp[1].CLK
CLK => Key_temp[0].CLK
CLK => Count[2].CLK
Dout[0] <= Key_temp[0].DB_MAX_OUTPUT_PORT_TYPE
Dout[1] <= Key_temp[1].DB_MAX_OUTPUT_PORT_TYPE
Dout[2] <= Key_temp[2].DB_MAX_OUTPUT_PORT_TYPE
Dout[3] <= Key_temp[3].DB_MAX_OUTPUT_PORT_TYPE
Dout[4] <= Key_temp[4].DB_MAX_OUTPUT_PORT_TYPE
Dout[5] <= reduce_or~2.DB_MAX_OUTPUT_PORT_TYPE
Dout[6] <= reduce_or~1.DB_MAX_OUTPUT_PORT_TYPE
Dout[7] <= reduce_or~0.DB_MAX_OUTPUT_PORT_TYPE
KC[0] <= KC~5
KC[1] <= KC~4
KC[2] <= KC~3
KR[0] <= KR~11
KR[1] <= KR~10
KR[2] <= KR~9
KR[3] <= KR~8
KR[4] <= KR~7
KR[5] <= KR~6
KP[0] => Decoder~0.IN5
KP[1] => Decoder~0.IN4
KP[2] => Decoder~0.IN3
KP[3] => Decoder~0.IN2
KP[4] => Decoder~0.IN1
KP[5] => Decoder~0.IN0
INT <= Equal~2.DB_MAX_OUTPUT_PORT_TYPE


|ad9851_2007|max195:inst21
COV <= COV~reg0.DB_MAX_OUTPUT_PORT_TYPE
CS => always2~0.IN0
RD => always2~0.IN1
Addr => always2~2.IN1
Addr => always2~1.IN1
D_out[0] <= D_out[0]~reg0.DB_MAX_OUTPUT_PORT_TYPE
D_out[1] <= D_out[1]~reg0.DB_MAX_OUTPUT_PORT_TYPE
D_out[2] <= D_out[2]~reg0.DB_MAX_OUTPUT_PORT_TYPE
D_out[3] <= D_out[3]~reg0.DB_MAX_OUTPUT_PORT_TYPE
D_out[4] <= D_out[4]~reg0.DB_MAX_OUTPUT_PORT_TYPE
D_out[5] <= D_out[5]~reg0.DB_MAX_OUTPUT_PORT_TYPE
D_out[6] <= D_out[6]~reg0.DB_MAX_OUTPUT_PORT_TYPE
D_out[7] <= D_out[7]~reg0.DB_MAX_OUTPUT_PORT_TYPE
D_in => DATA[15].DATAIN
D_in => DATA[14].DATAIN
D_in => DATA[13].DATAIN
D_in => DATA[12].DATAIN
D_in => DATA[11].DATAIN
D_in => DATA[10].DATAIN
D_in => DATA[9].DATAIN
D_in => DATA[8].DATAIN
D_in => DATA[7].DATAIN
D_in => DATA[6].DATAIN
D_in => DATA[5].DATAIN
D_in => DATA[4].DATAIN
D_in => DATA[3].DATAIN
D_in => DATA[2].DATAIN
D_in => DATA[1].DATAIN
D_in => DATA[0].DATAIN
CLK => CLK~0.IN1
INT <= INT~reg0.DB_MAX_OUTPUT_PORT_TYPE
CLK_MAX195 <= CLK_MAX195~reg0.DB_MAX_OUTPUT_PORT_TYPE


|ad9851_2007|max195:inst21|fp_2:fp_2_1
C_in => Cout.CLK
C_out <= Cout.DB_MAX_OUTPUT_PORT_TYPE


|ad9851_2007|fp_5:inst25
CLK_in => Cout[1].CLK
CLK_in => Cout[0].CLK
CLK_in => Cout[2].CLK
CLK_out <= Cout[2].DB_MAX_OUTPUT_PORT_TYPE


|ad9851_2007|max542:inst31
CLK => CLK~0.IN1
Addr => always0~2.IN1
Addr => always0~0.IN1
CS_in => always0~1.IN0
WR => always0~1.IN1
D_in[0] => D_temp[8].DATAIN
D_in[0] => D_temp[0].DATAIN
D_in[1] => D_temp[9].DATAIN
D_in[1] => D_temp[1].DATAIN
D_in[2] => D_temp[10].DATAIN
D_in[2] => D_temp[2].DATAIN
D_in[3] => D_temp[11].DATAIN
D_in[3] => D_temp[3].DATAIN
D_in[4] => D_temp[12].DATAIN
D_in[4] => D_temp[4].DATAIN
D_in[5] => D_temp[13].DATAIN
D_in[5] => D_temp[5].DATAIN
D_in[6] => D_temp[14].DATAIN
D_in[6] => D_temp[6].DATAIN
D_in[7] => D_temp[7].DATAIN
D_in[7] => D_temp[15].DATAIN
CS <= CS~reg0.DB_MAX_OUTPUT_PORT_TYPE
SCLK <= SCLK~reg0.DB_MAX_OUTPUT_PORT_TYPE
D_out <= D_out~reg0.DB_MAX_OUTPUT_PORT_TYPE


|ad9851_2007|max542:inst31|fp_2:fp_2_1
C_in => Cout.CLK
C_out <= Cout.DB_MAX_OUTPUT_PORT_TYPE


|ad9851_2007|lpm_rom1:inst17
address[0] => address[0]~11.IN1
address[1] => address[1]~10.IN1
address[2] => address[2]~9.IN1
address[3] => address[3]~8.IN1
address[4] => address[4]~7.IN1
address[5] => address[5]~6.IN1
address[6] => address[6]~5.IN1
address[7] => address[7]~4.IN1
address[8] => address[8]~3.IN1
address[9] => address[9]~2.IN1
address[10] => address[10]~1.IN1
address[11] => address[11]~0.IN1
clock => clock~0.IN1
q[0] <= altsyncram:altsyncram_component.q_a
q[1] <= altsyncram:altsyncram_component.q_a
q[2] <= altsyncram:altsyncram_component.q_a
q[3] <= altsyncram:altsyncram_component.q_a
q[4] <= altsyncram:altsyncram_component.q_a
q[5] <= altsyncram:altsyncram_component.q_a
q[6] <= altsyncram:altsyncram_component.q_a
q[7] <= altsyncram:altsyncram_component.q_a


|ad9851_2007|lpm_rom1:inst17|altsyncram:altsyncram_component
wren_a => ~NO_FANOUT~
wren_b => ~NO_FANOUT~
rden_b => ~NO_FANOUT~
data_a[0] => ~NO_FANOUT~
data_a[1] => ~NO_FANOUT~
data_a[2] => ~NO_FANOUT~
data_a[3] => ~NO_FANOUT~
data_a[4] => ~NO_FANOUT~
data_a[5] => ~NO_FANOUT~
data_a[6] => ~NO_FANOUT~
data_a[7] => ~NO_FANOUT~
data_b[0] => ~NO_FANOUT~
address_a[0] => altsyncram_qbs:auto_generated.address_a[0]
address_a[1] => altsyncram_qbs:auto_generated.address_a[1]
address_a[2] => altsyncram_qbs:auto_generated.address_a[2]
address_a[3] => altsyncram_qbs:auto_generated.address_a[3]
address_a[4] => altsyncram_qbs:auto_generated.address_a[4]
address_a[5] => altsyncram_qbs:auto_generated.address_a[5]
address_a[6] => altsyncram_qbs:auto_generated.address_a[6]
address_a[7] => altsyncram_qbs:auto_generated.address_a[7]
address_a[8] => altsyncram_qbs:auto_generated.address_a[8]
address_a[9] => altsyncram_qbs:auto_generated.address_a[9]
address_a[10] => altsyncram_qbs:auto_generated.address_a[10]
address_a[11] => altsyncram_qbs:auto_generated.address_a[11]
address_b[0] => ~NO_FANOUT~
addressstall_a => ~NO_FANOUT~
addressstall_b => ~NO_FANOUT~
clock0 => altsyncram_qbs:auto_generated.clock0
clock1 => ~NO_FANOUT~
clocken0 => ~NO_FANOUT~
clocken1 => ~NO_FANOUT~
aclr0 => ~NO_FANOUT~
aclr1 => ~NO_FANOUT~
byteena_a[0] => ~NO_FANOUT~
byteena_b[0] => ~NO_FANOUT~
q_a[0] <= altsyncram_qbs:auto_generated.q_a[0]
q_a[1] <= altsyncram_qbs:auto_generated.q_a[1]
q_a[2] <= altsyncram_qbs:auto_generated.q_a[2]
q_a[3] <= altsyncram_qbs:auto_generated.q_a[3]
q_a[4] <= altsyncram_qbs:auto_generated.q_a[4]
q_a[5] <= altsyncram_qbs:auto_generated.q_a[5]
q_a[6] <= altsyncram_qbs:auto_generated.q_a[6]
q_a[7] <= altsyncram_qbs:auto_generated.q_a[7]
q_b[0] <= <GND>


|ad9851_2007|lpm_rom1:inst17|altsyncram:altsyncram_component|altsyncram_qbs:auto_generated
address_a[0] => ram_block1a0.PORTAADDR
address_a[0] => ram_block1a1.PORTAADDR
address_a[0] => ram_block1a2.PORTAADDR
address_a[0] => ram_block1a3.PORTAADDR
address_a[0] => ram_block1a4.PORTAADDR
address_a[0] => ram_block1a5.PORTAADDR
address_a[0] => ram_block1a6.PORTAADDR
address_a[0] => ram_block1a7.PORTAADDR
address_a[1] => ram_block1a0.PORTAADDR1
address_a[1] => ram_block1a1.PORTAADDR1
address_a[1] => ram_block1a2.PORTAADDR1
address_a[1] => ram_block1a3.PORTAADDR1
address_a[1] => ram_block1a4.PORTAADDR1
address_a[1] => ram_block1a5.PORTAADDR1
address_a[1] => ram_block1a6.PORTAADDR1
address_a[1] => ram_block1a7.PORTAADDR1
address_a[2] => ram_block1a0.PORTAADDR2
address_a[2] => ram_block1a1.PORTAADDR2
address_a[2] => ram_block1a2.PORTAADDR2
address_a[2] => ram_block1a3.PORTAADDR2
address_a[2] => ram_block1a4.PORTAADDR2
address_a[2] => ram_block1a5.PORTAADDR2
address_a[2] => ram_block1a6.PORTAADDR2
address_a[2] => ram_block1a7.PORTAADDR2
address_a[3] => ram_block1a0.PORTAADDR3
address_a[3] => ram_block1a1.PORTAADDR3
address_a[3] => ram_block1a2.PORTAADDR3
address_a[3] => ram_block1a3.PORTAADDR3
address_a[3] => ram_block1a4.PORTAADDR3
address_a[3] => ram_block1a5.PORTAADDR3
address_a[3] => ram_block1a6.PORTAADDR3
address_a[3] => ram_block1a7.PORTAADDR3
address_a[4] => ram_block1a0.PORTAADDR4
address_a[4] => ram_block1a1.PORTAADDR4
address_a[4] => ram_block1a2.PORTAADDR4
address_a[4] => ram_block1a3.PORTAADDR4
address_a[4] => ram_block1a4.PORTAADDR4
address_a[4] => ram_block1a5.PORTAADDR4
address_a[4] => ram_block1a6.PORTAADDR4
address_a[4] => ram_block1a7.PORTAADDR4
address_a[5] => ram_block1a0.PORTAADDR5
address_a[5] => ram_block1a1.PORTAADDR5
address_a[5] => ram_block1a2.PORTAADDR5
address_a[5] => ram_block1a3.PORTAADDR5
address_a[5] => ram_block1a4.PORTAADDR5
address_a[5] => ram_block1a5.PORTAADDR5
address_a[5] => ram_block1a6.PORTAADDR5
address_a[5] => ram_block1a7.PORTAADDR5
address_a[6] => ram_block1a0.PORTAADDR6
address_a[6] => ram_block1a1.PORTAADDR6
address_a[6] => ram_block1a2.PORTAADDR6
address_a[6] => ram_block1a3.PORTAADDR6
address_a[6] => ram_block1a4.PORTAADDR6
address_a[6] => ram_block1a5.PORTAADDR6
address_a[6] => ram_block1a6.PORTAADDR6
address_a[6] => ram_block1a7.PORTAADDR6
address_a[7] => ram_block1a0.PORTAADDR7
address_a[7] => ram_block1a1.PORTAADDR7
address_a[7] => ram_block1a2.PORTAADDR7
address_a[7] => ram_block1a3.PORTAADDR7
address_a[7] => ram_block1a4.PORTAADDR7
address_a[7] => ram_block1a5.PORTAADDR7
address_a[7] => ram_block1a6.PORTAADDR7
address_a[7] => ram_block1a7.PORTAADDR7
address_a[8] => ram_block1a0.PORTAADDR8
address_a[8] => ram_block1a1.PORTAADDR8
address_a[8] => ram_block1a2.PORTAADDR8
address_a[8] => ram_block1a3.PORTAADDR8
address_a[8] => ram_block1a4.PORTAADDR8
address_a[8] => ram_block1a5.PORTAADDR8
address_a[8] => ram_block1a6.PORTAADDR8
address_a[8] => ram_block1a7.PORTAADDR8
address_a[9] => ram_block1a0.PORTAADDR9
address_a[9] => ram_block1a1.PORTAADDR9
address_a[9] => ram_block1a2.PORTAADDR9
address_a[9] => ram_block1a3.PORTAADDR9
address_a[9] => ram_block1a4.PORTAADDR9
address_a[9] => ram_block1a5.PORTAADDR9
address_a[9] => ram_block1a6.PORTAADDR9
address_a[9] => ram_block1a7.PORTAADDR9
address_a[10] => ram_block1a0.PORTAADDR10
address_a[10] => ram_block1a1.PORTAADDR10
address_a[10] => ram_block1a2.PORTAADDR10
address_a[10] => ram_block1a3.PORTAADDR10
address_a[10] => ram_block1a4.PORTAADDR10
address_a[10] => ram_block1a5.PORTAADDR10
address_a[10] => ram_block1a6.PORTAADDR10
address_a[10] => ram_block1a7.PORTAADDR10
address_a[11] => ram_block1a0.PORTAADDR11
address_a[11] => ram_block1a1.PORTAADDR11
address_a[11] => ram_block1a2.PORTAADDR11
address_a[11] => ram_block1a3.PORTAADDR11
address_a[11] => ram_block1a4.PORTAADDR11
address_a[11] => ram_block1a5.PORTAADDR11
address_a[11] => ram_block1a6.PORTAADDR11
address_a[11] => ram_block1a7.PORTAADDR11
clock0 => ram_block1a0.CLK0
clock0 => ram_block1a1.CLK0
clock0 => ram_block1a2.CLK0
clock0 => ram_block1a3.CLK0
clock0 => ram_block1a4.CLK0
clock0 => ram_block1a5.CLK0
clock0 => ram_block1a6.CLK0
clock0 => ram_block1a7.CLK0
q_a[0] <= ram_block1a0.PORTADATAOUT
q_a[1] <= ram_block1a1.PORTADATAOUT
q_a[2] <= ram_block1a2.PORTADATAOUT
q_a[3] <= ram_block1a3.PORTADATAOUT
q_a[4] <= ram_block1a4.PORTADATAOUT
q_a[5] <= ram_block1a5.PORTADATAOUT
q_a[6] <= ram_block1a6.PORTADATAOUT
q_a[7] <= ram_block1a7.PORTADATAOUT


|ad9851_2007|DDS_4K:inst14
Din[0] => K[24].DATAIN
Din[0] => K[16].DATAIN
Din[0] => K[8].DATAIN
Din[0] => K[0].DATAIN
Din[1] => K[25].DATAIN
Din[1] => K[17].DATAIN
Din[1] => K[9].DATAIN
Din[1] => K[1].DATAIN
Din[2] => K[26].DATAIN
Din[2] => K[18].DATAIN
Din[2] => K[10].DATAIN
Din[2] => K[2].DATAIN
Din[3] => K[19].DATAIN
Din[3] => K[11].DATAIN
Din[3] => K[3].DATAIN
Din[3] => K[27].DATAIN
Din[4] => K[20].DATAIN
Din[4] => K[12].DATAIN
Din[4] => K[4].DATAIN
Din[5] => K[21].DATAIN
Din[5] => K[13].DATAIN
Din[5] => K[5].DATAIN
Din[6] => K[22].DATAIN
Din[6] => K[14].DATAIN
Din[6] => K[6].DATAIN
Din[7] => K[23].DATAIN
Din[7] => K[15].DATAIN
Din[7] => K[7].DATAIN
WR => always0~0.IN1
CS => always0~0.IN0
CLK => K[26].CLK
CLK => K[25].CLK
CLK => K[24].CLK
CLK => K[23].CLK
CLK => K[22].CLK
CLK => K[21].CLK
CLK => K[20].CLK
CLK => K[19].CLK
CLK => K[18].CLK
CLK => K[17].CLK
CLK => K[16].CLK
CLK => K[15].CLK
CLK => K[14].CLK
CLK => K[13].CLK
CLK => K[12].CLK
CLK => K[11].CLK
CLK => K[10].CLK
CLK => K[9].CLK
CLK => K[8].CLK
CLK => K[7].CLK
CLK => K[6].CLK
CLK => K[5].CLK
CLK => K[4].CLK
CLK => K[3].CLK
CLK => K[2].CLK
CLK => K[1].CLK
CLK => K[0].CLK
CLK => ACC[31].CLK
CLK => ACC[30].CLK
CLK => ACC[29].CLK
CLK => ACC[28].CLK
CLK => ACC[27].CLK
CLK => ACC[26].CLK
CLK => ACC[25].CLK
CLK => ACC[24].CLK
CLK => ACC[23].CLK
CLK => ACC[22].CLK
CLK => ACC[21].CLK
CLK => ACC[20].CLK
CLK => ACC[19].CLK
CLK => ACC[18].CLK
CLK => ACC[17].CLK
CLK => ACC[16].CLK
CLK => ACC[15].CLK
CLK => ACC[14].CLK
CLK => ACC[13].CLK
CLK => ACC[12].CLK
CLK => ACC[11].CLK
CLK => ACC[10].CLK
CLK => ACC[9].CLK
CLK => ACC[8].CLK
CLK => ACC[7].CLK
CLK => ACC[6].CLK
CLK => ACC[5].CLK
CLK => ACC[4].CLK
CLK => ACC[3].CLK
CLK => ACC[2].CLK
CLK => ACC[1].CLK
CLK => ACC[0].CLK
CLK => K[27].CLK
Addr[0] => Decoder~0.IN1
Addr[1] => Decoder~0.IN0
Aout[0] <= ACC[20].DB_MAX_OUTPUT_PORT_TYPE
Aout[1] <= ACC[21].DB_MAX_OUTPUT_PORT_TYPE
Aout[2] <= ACC[22].DB_MAX_OUTPUT_PORT_TYPE
Aout[3] <= ACC[23].DB_MAX_OUTPUT_PORT_TYPE
Aout[4] <= ACC[24].DB_MAX_OUTPUT_PORT_TYPE
Aout[5] <= ACC[25].DB_MAX_OUTPUT_PORT_TYPE
Aout[6] <= ACC[26].DB_MAX_OUTPUT_PORT_TYPE
Aout[7] <= ACC[27].DB_MAX_OUTPUT_PORT_TYPE
Aout[8] <= ACC[28].DB_MAX_OUTPUT_PORT_TYPE
Aout[9] <= ACC[29].DB_MAX_OUTPUT_PORT_TYPE
Aout[10] <= ACC[30].DB_MAX_OUTPUT_PORT_TYPE
Aout[11] <= ACC[31].DB_MAX_OUTPUT_PORT_TYPE


|ad9851_2007|data_ctl:inst30
CS => DOUT~0.