ad9851_2007.hier_info

计算实用教程adadad9851实用教程

sout[8] <= sout_node[8].DB_MAX_OUTPUT_PORT_TYPE
sout[9] <= sout_node[9].DB_MAX_OUTPUT_PORT_TYPE
sout[10] <= sout_node[10].DB_MAX_OUTPUT_PORT_TYPE
sout[11] <= sout_node[11].DB_MAX_OUTPUT_PORT_TYPE
sout[12] <= sout_node[12].DB_MAX_OUTPUT_PORT_TYPE
sout[13] <= sout_node[13].DB_MAX_OUTPUT_PORT_TYPE
sout[14] <= sout_node[14].DB_MAX_OUTPUT_PORT_TYPE
sout[15] <= sout_node[15].DB_MAX_OUTPUT_PORT_TYPE
cout[0] <= cout[0]~15.DB_MAX_OUTPUT_PORT_TYPE
cout[1] <= cout[1]~14.DB_MAX_OUTPUT_PORT_TYPE
cout[2] <= cout[2]~13.DB_MAX_OUTPUT_PORT_TYPE
cout[3] <= cout[3]~12.DB_MAX_OUTPUT_PORT_TYPE
cout[4] <= cout[4]~11.DB_MAX_OUTPUT_PORT_TYPE
cout[5] <= cout[5]~10.DB_MAX_OUTPUT_PORT_TYPE
cout[6] <= cout[6]~9.DB_MAX_OUTPUT_PORT_TYPE
cout[7] <= cout[7]~8.DB_MAX_OUTPUT_PORT_TYPE
cout[8] <= cout[8]~7.DB_MAX_OUTPUT_PORT_TYPE
cout[9] <= cout[9]~6.DB_MAX_OUTPUT_PORT_TYPE
cout[10] <= cout[10]~5.DB_MAX_OUTPUT_PORT_TYPE
cout[11] <= cout[11]~4.DB_MAX_OUTPUT_PORT_TYPE
cout[12] <= cout[12]~3.DB_MAX_OUTPUT_PORT_TYPE
cout[13] <= cout[13]~2.DB_MAX_OUTPUT_PORT_TYPE
cout[14] <= cout[14]~1.DB_MAX_OUTPUT_PORT_TYPE
cout[15] <= cout[15]~0.DB_MAX_OUTPUT_PORT_TYPE


|ad9851_2007|lpm_mult0:inst15|lpm_mult:lpm_mult_component|multcore:mult_core|mpar_add:padder|lpm_add_sub:adder[0]|altshift:result_ext_latency_ffs
data[0] => result[0].DATAIN
data[1] => result[1].DATAIN
data[2] => result[2].DATAIN
data[3] => result[3].DATAIN
data[4] => result[4].DATAIN
data[5] => result[5].DATAIN
data[6] => result[6].DATAIN
data[7] => result[7].DATAIN
data[8] => result[8].DATAIN
data[9] => result[9].DATAIN
data[10] => result[10].DATAIN
data[11] => result[11].DATAIN
data[12] => result[12].DATAIN
data[13] => result[13].DATAIN
data[14] => result[14].DATAIN
data[15] => result[15].DATAIN
clock => ~NO_FANOUT~
aclr => ~NO_FANOUT~
clken => ~NO_FANOUT~
result[0] <= data[0].DB_MAX_OUTPUT_PORT_TYPE
result[1] <= data[1].DB_MAX_OUTPUT_PORT_TYPE
result[2] <= data[2].DB_MAX_OUTPUT_PORT_TYPE
result[3] <= data[3].DB_MAX_OUTPUT_PORT_TYPE
result[4] <= data[4].DB_MAX_OUTPUT_PORT_TYPE
result[5] <= data[5].DB_MAX_OUTPUT_PORT_TYPE
result[6] <= data[6].DB_MAX_OUTPUT_PORT_TYPE
result[7] <= data[7].DB_MAX_OUTPUT_PORT_TYPE
result[8] <= data[8].DB_MAX_OUTPUT_PORT_TYPE
result[9] <= data[9].DB_MAX_OUTPUT_PORT_TYPE
result[10] <= data[10].DB_MAX_OUTPUT_PORT_TYPE
result[11] <= data[11].DB_MAX_OUTPUT_PORT_TYPE
result[12] <= data[12].DB_MAX_OUTPUT_PORT_TYPE
result[13] <= data[13].DB_MAX_OUTPUT_PORT_TYPE
result[14] <= data[14].DB_MAX_OUTPUT_PORT_TYPE
result[15] <= data[15].DB_MAX_OUTPUT_PORT_TYPE


|ad9851_2007|lpm_mult0:inst15|lpm_mult:lpm_mult_component|multcore:mult_core|mpar_add:padder|lpm_add_sub:adder[0]|altshift:carry_ext_latency_ffs
data[0] => result[0].DATAIN
clock => ~NO_FANOUT~
aclr => ~NO_FANOUT~
clken => ~NO_FANOUT~
result[0] <= data[0].DB_MAX_OUTPUT_PORT_TYPE


|ad9851_2007|lpm_mult0:inst15|lpm_mult:lpm_mult_component|multcore:mult_core|mpar_add:padder|lpm_add_sub:adder[0]|altshift:oflow_ext_latency_ffs
data[0] => result[0].DATAIN
clock => ~NO_FANOUT~
aclr => ~NO_FANOUT~
clken => ~NO_FANOUT~
result[0] <= data[0].DB_MAX_OUTPUT_PORT_TYPE


|ad9851_2007|lpm_mult0:inst15|lpm_mult:lpm_mult_component|altshift:external_latency_ffs
data[0] => result[0].DATAIN
data[1] => result[1].DATAIN
data[2] => result[2].DATAIN
data[3] => result[3].DATAIN
data[4] => result[4].DATAIN
data[5] => result[5].DATAIN
data[6] => result[6].DATAIN
data[7] => result[7].DATAIN
data[8] => result[8].DATAIN
data[9] => result[9].DATAIN
data[10] => result[10].DATAIN
data[11] => result[11].DATAIN
data[12] => result[12].DATAIN
data[13] => result[13].DATAIN
data[14] => result[14].DATAIN
data[15] => result[15].DATAIN
data[16] => result[16].DATAIN
data[17] => result[17].DATAIN
data[18] => result[18].DATAIN
data[19] => result[19].DATAIN
clock => ~NO_FANOUT~
aclr => ~NO_FANOUT~
clken => ~NO_FANOUT~
result[0] <= data[0].DB_MAX_OUTPUT_PORT_TYPE
result[1] <= data[1].DB_MAX_OUTPUT_PORT_TYPE
result[2] <= data[2].DB_MAX_OUTPUT_PORT_TYPE
result[3] <= data[3].DB_MAX_OUTPUT_PORT_TYPE
result[4] <= data[4].DB_MAX_OUTPUT_PORT_TYPE
result[5] <= data[5].DB_MAX_OUTPUT_PORT_TYPE
result[6] <= data[6].DB_MAX_OUTPUT_PORT_TYPE
result[7] <= data[7].DB_MAX_OUTPUT_PORT_TYPE
result[8] <= data[8].DB_MAX_OUTPUT_PORT_TYPE
result[9] <= data[9].DB_MAX_OUTPUT_PORT_TYPE
result[10] <= data[10].DB_MAX_OUTPUT_PORT_TYPE
result[11] <= data[11].DB_MAX_OUTPUT_PORT_TYPE
result[12] <= data[12].DB_MAX_OUTPUT_PORT_TYPE
result[13] <= data[13].DB_MAX_OUTPUT_PORT_TYPE
result[14] <= data[14].DB_MAX_OUTPUT_PORT_TYPE
result[15] <= data[15].DB_MAX_OUTPUT_PORT_TYPE
result[16] <= data[16].DB_MAX_OUTPUT_PORT_TYPE
result[17] <= data[17].DB_MAX_OUTPUT_PORT_TYPE
result[18] <= data[18].DB_MAX_OUTPUT_PORT_TYPE
result[19] <= data[19].DB_MAX_OUTPUT_PORT_TYPE


|ad9851_2007|lpm_rom0:inst11
address[0] => address[0]~7.IN1
address[1] => address[1]~6.IN1
address[2] => address[2]~5.IN1
address[3] => address[3]~4.IN1
address[4] => address[4]~3.IN1
address[5] => address[5]~2.IN1
address[6] => address[6]~1.IN1
address[7] => address[7]~0.IN1
clock => clock~0.IN1
q[0] <= altsyncram:altsyncram_component.q_a
q[1] <= altsyncram:altsyncram_component.q_a
q[2] <= altsyncram:altsyncram_component.q_a
q[3] <= altsyncram:altsyncram_component.q_a
q[4] <= altsyncram:altsyncram_component.q_a
q[5] <= altsyncram:altsyncram_component.q_a
q[6] <= altsyncram:altsyncram_component.q_a
q[7] <= altsyncram:altsyncram_component.q_a


|ad9851_2007|lpm_rom0:inst11|altsyncram:altsyncram_component
wren_a => ~NO_FANOUT~
wren_b => ~NO_FANOUT~
rden_b => ~NO_FANOUT~
data_a[0] => ~NO_FANOUT~
data_a[1] => ~NO_FANOUT~
data_a[2] => ~NO_FANOUT~
data_a[3] => ~NO_FANOUT~
data_a[4] => ~NO_FANOUT~
data_a[5] => ~NO_FANOUT~
data_a[6] => ~NO_FANOUT~
data_a[7] => ~NO_FANOUT~
data_b[0] => ~NO_FANOUT~
address_a[0] => altsyncram_n8s:auto_generated.address_a[0]
address_a[1] => altsyncram_n8s:auto_generated.address_a[1]
address_a[2] => altsyncram_n8s:auto_generated.address_a[2]
address_a[3] => altsyncram_n8s:auto_generated.address_a[3]
address_a[4] => altsyncram_n8s:auto_generated.address_a[4]
address_a[5] => altsyncram_n8s:auto_generated.address_a[5]
address_a[6] => altsyncram_n8s:auto_generated.address_a[6]
address_a[7] => altsyncram_n8s:auto_generated.address_a[7]
address_b[0] => ~NO_FANOUT~
addressstall_a => ~NO_FANOUT~
addressstall_b => ~NO_FANOUT~
clock0 => altsyncram_n8s:auto_generated.clock0
clock1 => ~NO_FANOUT~
clocken0 => ~NO_FANOUT~
clocken1 => ~NO_FANOUT~
aclr0 => ~NO_FANOUT~
aclr1 => ~NO_FANOUT~
byteena_a[0] => ~NO_FANOUT~
byteena_b[0] => ~NO_FANOUT~
q_a[0] <= altsyncram_n8s:auto_generated.q_a[0]
q_a[1] <= altsyncram_n8s:auto_generated.q_a[1]
q_a[2] <= altsyncram_n8s:auto_generated.q_a[2]
q_a[3] <= altsyncram_n8s:auto_generated.q_a[3]
q_a[4] <= altsyncram_n8s:auto_generated.q_a[4]
q_a[5] <= altsyncram_n8s:auto_generated.q_a[5]
q_a[6] <= altsyncram_n8s:auto_generated.q_a[6]
q_a[7] <= altsyncram_n8s:auto_generated.q_a[7]
q_b[0] <= <GND>


|ad9851_2007|lpm_rom0:inst11|altsyncram:altsyncram_component|altsyncram_n8s:auto_generated
address_a[0] => ram_block1a0.PORTAADDR
address_a[0] => ram_block1a1.PORTAADDR
address_a[0] => ram_block1a2.PORTAADDR
address_a[0] => ram_block1a3.PORTAADDR
address_a[0] => ram_block1a4.PORTAADDR
address_a[0] => ram_block1a5.PORTAADDR
address_a[0] => ram_block1a6.PORTAADDR
address_a[0] => ram_block1a7.PORTAADDR
address_a[1] => ram_block1a0.PORTAADDR1
address_a[1] => ram_block1a1.PORTAADDR1
address_a[1] => ram_block1a2.PORTAADDR1
address_a[1] => ram_block1a3.PORTAADDR1
address_a[1] => ram_block1a4.PORTAADDR1
address_a[1] => ram_block1a5.PORTAADDR1
address_a[1] => ram_block1a6.PORTAADDR1
address_a[1] => ram_block1a7.PORTAADDR1
address_a[2] => ram_block1a0.PORTAADDR2
address_a[2] => ram_block1a1.PORTAADDR2
address_a[2] => ram_block1a2.PORTAADDR2
address_a[2] => ram_block1a3.PORTAADDR2
address_a[2] => ram_block1a4.PORTAADDR2
address_a[2] => ram_block1a5.PORTAADDR2
address_a[2] => ram_block1a6.PORTAADDR2
address_a[2] => ram_block1a7.PORTAADDR2
address_a[3] => ram_block1a0.PORTAADDR3
address_a[3] => ram_block1a1.PORTAADDR3
address_a[3] => ram_block1a2.PORTAADDR3
address_a[3] => ram_block1a3.PORTAADDR3
address_a[3] => ram_block1a4.PORTAADDR3
address_a[3] => ram_block1a5.PORTAADDR3
address_a[3] => ram_block1a6.PORTAADDR3
address_a[3] => ram_block1a7.PORTAADDR3
address_a[4] => ram_block1a0.PORTAADDR4
address_a[4] => ram_block1a1.PORTAADDR4
address_a[4] => ram_block1a2.PORTAADDR4
address_a[4] => ram_block1a3.PORTAADDR4
address_a[4] => ram_block1a4.PORTAADDR4
address_a[4] => ram_block1a5.PORTAADDR4
address_a[4] => ram_block1a6.PORTAADDR4
address_a[4] => ram_block1a7.PORTAADDR4
address_a[5] => ram_block1a0.PORTAADDR5
address_a[5] => ram_block1a1.PORTAADDR5
address_a[5] => ram_block1a2.PORTAADDR5
address_a[5] => ram_block1a3.PORTAADDR5
address_a[5] => ram_block1a4.PORTAADDR5
address_a[5] => ram_block1a5.PORTAADDR5
address_a[5] => ram_block1a6.PORTAADDR5
address_a[5] => ram_block1a7.PORTAADDR5
address_a[6] => ram_block1a0.PORTAADDR6
address_a[6] => ram_block1a1.PORTAADDR6
address_a[6] => ram_block1a2.PORTAADDR6
address_a[6] => ram_block1a3.PORTAADDR6
address_a[6] => ram_block1a4.PORTAADDR6
address_a[6] => ram_block1a5.PORTAADDR6
address_a[6] => ram_block1a6.PORTAADDR6
address_a[6] => ram_block1a7.PORTAADDR6
address_a[7] => ram_block1a0.PORTAADDR7
address_a[7] => ram_block1a1.PORTAADDR7
address_a[7] => ram_block1a2.PORTAADDR7
address_a[7] => ram_block1a3.PORTAADDR7
address_a[7] => ram_block1a4.PORTAADDR7
address_a[7] => ram_block1a5.PORTAADDR7
address_a[7] => ram_block1a6.PORTAADDR7
address_a[7] => ram_block1a7.PORTAADDR7
clock0 => ram_block1a0.CLK0
clock0 => ram_block1a1.CLK0
clock0 => ram_block1a2.CLK0
clock0 => ram_block1a3.CLK0
clock0 => ram_block1a4.CLK0
clock0 => ram_block1a5.CLK0
clock0 => ram_block1a6.CLK0
clock0 => ram_block1a7.CLK0
q_a[0] <= ram_block1a0.PORTADATAOUT
q_a[1] <= ram_block1a1.PORTADATAOUT
q_a[2] <= ram_block1a2.PORTADATAOUT
q_a[3] <= ram_block1a3.PORTADATAOUT
q_a[4] <= ram_block1a4.PORTADATAOUT
q_a[5] <= ram_block1a5.PORTADATAOUT
q_a[6] <= ram_block1a6.PORTADATAOUT
q_a[7] <= ram_block1a7.PORTADATAOUT


|ad9851_2007|ROM256ADDR:inst10
CLK => Aout[6]~reg0.CLK
CLK => Aout[5]~reg0.CLK
CLK => Aout[4]~reg0.CLK
CLK => Aout[3]~reg0.CLK
CLK => Aout[2]~reg0.CLK
CLK => Aout[1]~reg0.CLK
CLK => Aout[0]~reg0.CLK
CLK => Aout[7]~reg0.CLK
Aout[0] <= Aout[0]~reg0.DB_MAX_OUTPUT_PORT_TYPE
Aout[1] <= Aout[1]~reg0.DB_MAX_OUTPUT_PORT_TYPE
Aout[2] <= Aout[2]~reg0.DB_MAX_OUTPUT_PORT_TYPE
Aout[3] <= Aout[3]~reg0.DB_MAX_OUTPUT_PORT_TYPE
Aout[4] <= Aout[4]~reg0.DB_MAX_OUTPUT_PORT_TYPE
Aout[5] <= Aout[5]~reg0.DB_MAX_OUTPUT_PORT_TYPE
Aout[6] <= Aout[6]~reg0.DB_MAX_OUTPUT_PORT_TYPE
Aout[7] <= Aout[7]~reg0.DB_MAX_OUTPUT_PORT_TYPE


|ad9851_2007|fp_5:inst9
CLK_in => Cout[1].CLK
CLK_in => Cout[0].CLK
CLK_in => Cout[2].CLK
CLK_out <= Cout[2].DB_MAX_OUTPUT_PORT_TYPE


|ad9851_2007|fp_5:inst8
CLK_in => Cout[1].CLK
CLK_in => Cout[0].CLK
CLK_in => Cout[2].CLK
CLK_out <= Cout[2].DB_MAX_OUTPUT_PORT_TYPE


|ad9851_2007|fp_5:inst7
CLK_in => Cout[1].CLK
CLK_in => Cout[0].CLK
CLK_in => Cout[2].CLK
CLK_out <= Cout[2].DB_MAX_OUTPUT_PORT_TYPE


|ad9851_2007|altpll0:inst6
inclk0 => sub_wire3[0].IN1
c0 <= altpll:altpll_component.clk


|ad9851_2007|altpll0:inst6|altpll:altpll_component
inclk[0] => pll.CLK
inclk[1] => pll.CLK1
fbin => ~NO_FANOUT~
pllena => ~NO_FANOUT~
clkswitch => ~NO_FANOUT~
areset => ~NO_FANOUT~
pfdena => ~NO_FANOUT~
clkena[0] => ~NO_FANOUT~
clkena[1] => ~NO_FANOUT~
clkena[2] => ~NO_FANOUT~
clkena[3] => ~NO_FANOUT~
clkena[4] => ~NO_FANOUT~
clkena[5] => ~NO_FANOUT~
extclkena[0] => ~NO_FANOUT~
extclkena[1] => ~NO_FANOUT~
extclkena[2] => ~NO_FANOUT~
extclkena[3] => ~NO_FANOUT~
scanclk => ~NO_FANOUT~
scanaclr => ~NO_FANOUT~
scanread => ~NO_FANOUT~
scanwrite => ~NO_FANOUT~
scandata => ~NO_FANOUT~
clk[0] <= pll.CLK
clk[1] <= pll.CLK1
clk[2] <= pll.CLK2
clk[3] <= pll.CLK3
clk[4] <= pll.CLK4
clk[5] <= pll.CLK5
extclk[0] <= <GND>
extclk[1] <= <GND>
extclk[2] <= <GND>
extclk[3] <= <GND>
clkbad[0] <= <GND>
clkbad[1] <= <GND>
enable1 <= <GND>
enable0 <= <GND>
activeclock <= <GND>
clkloss <= <GND>
locked <= <GND>
scandataout <= <GND>
scandone <= <GND>
sclkout0 <= <GND>
sclkout1 <= <GND>


|ad9851_2007|dac0832:inst20
data_in[0] => data_out[0]$latch.DATAIN
data_in[1] => data_out[1]$latch.DATAIN
data_in[2] => data_out[2]$latch.DATAIN
data_in[3] => data_out[3]$latch.DATAIN
data_in[4] => data_out[4]$latch.DATAIN
data_in[5] => data_out[5]$latch.DATAIN
data_in[6] => data_out[6]$latch.DATAIN
data_in[7] => data_out[7]$latch.DATAIN
wr => WR_OUT.DATAIN
wr => always0~0.IN0
cs => CS_OUT.DATAIN
cs => always0~0.IN1
data_out[0] <= data_out[0]$latch.DB_MAX_OUTPUT_PORT_TYPE
data_out[1] <= data_out[1]$latch.DB_MAX_OUTPUT_PORT_TYPE
data_out[2] <= data_out[2]$latch.DB_MAX_OUTPUT_PORT_TYPE
data_out[3] <= data_out[3]$latch.DB_MAX_OUTPUT_PORT_TYPE
data_out[4] <= data_out[4]$latch.DB_MAX_OUTPUT_PORT_TYPE
data_out[5] <= data_out[5]$latch.DB_MAX_OUTPUT_PORT_TYPE
data_out[6] <= data_out[6]$latch.DB_MAX_OUTPUT_PORT_TYPE
data_out[7] <= data_out[7]$latch.DB_MAX_OUTPUT_PORT_TYPE
WR_OUT <= wr.DB_MAX_OUTPUT_PORT_TYPE
CS_OUT <= cs.DB_MAX_OUTPUT_PORT_TYPE


|ad9851_2007|ScanKey:inst29
CS => ~NO_FANOUT~
RD => ~NO_FANOUT~
CLK => Count[1].CLK
CLK => Count[0].CLK
CLK => KC_out[2].CLK
CLK => KC_out[1].CLK
CLK => KC_out[0].CLK
CLK => KR_out[5].CLK
CLK => KR_out[4].CLK
CLK => KR_out[3].CLK
CLK => KR_out[2].CLK
CLK => KR_out[1].CLK
CLK => KR_out[0].CLK
CLK => KC_temp[2].CLK
CLK => KC_temp[1].CLK
CLK => KC_temp[0].CLK
CLK => KR_temp[5].CLK
CLK => KR_temp[4].CLK
CLK => KR_temp[3].CLK
CLK => KR_temp[2].CLK