📄 module_9851.v
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module module_9851(
CLK, //CLK for this module 10 MHz
Din, //Data input port from MCU
WR, //WR signal from MCU
CS, //CS signal from MCU
Addr, //Address from MCU to choose the very reg group
Dout, //Data output port to AD9851
FQD, //Frequence data update signal to AD9851, rising edge
RST, //RESET signal to AD9851, high level
WCK, //Write clk to AD9851, rising edge
FM,
FM_SEL, //0:10KHZ;1:5KHZ
Code_in,
P_ASK
);
input [7:0] Din;
input CLK;
input WR;
input CS;
input [3:0] Addr;
input [19:0] FM;
input FM_SEL;
input Code_in;
output FQD;
output WCK;
output [7:0] Dout;
output RST;
output P_ASK;
reg FQD;
reg WCK;
reg RST;
reg[7:0] Dout;
reg[31:0] FM_TEMP;
reg[2:0] CTR; //1: sinwave output 2:FM mode 3:FSK mode 0:Stop write
reg[31:0] FRE1;
reg[31:0] FRE2;
reg[5:0] Count1;
reg[5:0] Count2;
reg[7:0] Count3;
reg[19:0] FM_DDS;
assign P_ASK=((CTR==3)||(CTR==4)||(CTR==5))?1:0;
always@(posedge CLK)
begin
if((!CS)&(!WR))
begin
case(Addr)
4'h0:FRE1[7:0]<=Din;
4'h1:FRE1[15:8]<=Din;
4'h2:FRE1[23:16]<=Din;
4'h3:FRE1[31:24]<=Din;
4'h5:FRE2[7:0]<=Din;
4'h6:FRE2[15:8]<=Din;
4'h7:FRE2[23:16]<=Din;
4'h8:FRE2[31:24]<=Din;
4'h4:CTR[2:0]<=Din[2:0];
endcase
end
if(CS)
begin
if(CTR==1) //1: sinwave output
Count1<=Count1+3'd1;
else
Count1<=0;
if(CTR==1)
begin
case(Count1)
5'd1:begin
WCK<=0;
FQD<=0;
// Count1<=2;
RST<=1;
end
//5'd3:begin
// FM_DDS<=FM;
// Count1<=4;
// end
// 5'd5:begin
// FM_TEMP<=FRE1;//+FM_DDS;
// Count1<=6;
// end
5'd12:begin
RST<=0;
// Count1<=13;
end
5'd15:begin
Dout<=8'h01;
// Count1<=16;
end
5'd16:begin
WCK<=1;
// Count1<=17;
end
5'd17:begin
Dout<=FRE1[31:24];//8'h00;//
WCK<=0;
// Count1<=18;
end
5'd18:begin
WCK<=1;
// Count1<=19;
end
5'd19:begin
Dout<=FRE1[23:16];//8'h01;//
WCK<=0;
// Count1<=20;
end
5'd20:begin
WCK<=1;
// Count1<=21;
end
5'd21:begin
Dout<=FRE1[15:8];//8'h01;//
WCK<=0;
// Count1<=22;
end
5'd22:begin
WCK<=1;
// Count1<=23;
end
5'd23:begin
Dout<=FRE1[7:0];//8'h01;//
WCK<=0;
// Count1<=24;
end
5'd24:begin
WCK<=1;
// Count1<=25;
end
5'd25:begin
WCK<=0;
// Count1<=26;
end
5'd26:begin
FQD<=1;
// Count1<=27;
end
5'd27:begin
CTR<=0;
// Count1<=28;
end
5'd30:begin
FQD<=0;
// Count1<=2;
end
// default:Count1<=Count1+3'd1;
endcase
end
if(CTR==2) // 2:FM mode
Count2=Count2+3'd1;
// else
// Count2<=0;
// if(CTR==2)
begin
case(Count2)
5'd0:begin
WCK<=0;
FQD<=0;
// Count1<=2;
// RST<=1;
end
5'd3:begin
FM_DDS<=FM;
// Count1<=4;
end
5'd5:begin
if(FM_SEL==1)
FM_TEMP<=FRE1+FM_DDS[19:1];
else
FM_TEMP<=FRE1+FM_DDS[19:0];
// Count1<=6;
end
5'd12:begin
RST<=0;
// Count1<=13;
end
5'd15:begin
Dout<=8'h21;
// Count1<=16;
end
5'd16:begin
WCK<=1;
// Count1<=17;
end
5'd17:begin
Dout<=FM_TEMP[31:24];//8'h00;//
WCK<=0;
// Count1<=18;
end
5'd18:begin
WCK<=1;
// Count1<=19;
end
5'd19:begin
Dout<=FM_TEMP[23:16];//8'h01;//
WCK<=0;
// Count1<=20;
end
5'd20:begin
WCK<=1;
// Count1<=21;
end
5'd21:begin
Dout<=FM_TEMP[15:8];//8'h01;//
WCK<=0;
// Count1<=22;
end
5'd22:begin
WCK<=1;
// Count1<=23;
end
5'd23:begin
Dout<=FM_TEMP[7:0];//8'h01;//
WCK<=0;
// Count1<=24;
end
5'd24:begin
WCK<=1;
// Count1<=25;
end
5'd25:begin
WCK<=0;
// Count1<=26;
end
5'd27:begin
FQD<=1;
// Count1<=27;
end
//5'd27:begin
// CTR<=0;
// end
5'd31:begin
FQD<=0;
// Count1<=2;
end
// default:Count1<=Count1+3'd1;
endcase
end
if(CTR==3||CTR==4||CTR==5) // 3:ASK mode
Count3=Count3+3'd1;
// else
// Count2<=0;
// if(CTR==2)
begin
case(Count3)
7'd0:begin
WCK<=0;
FQD<=0;
// Count1<=2;
// RST<=1;
end
7'd5:begin
if(CTR==3&&Code_in==1)
FM_TEMP<=FRE1;
else if(CTR==3&&Code_in==0)
FM_TEMP<=0;
else if(CTR==4&&Code_in==1)
FM_TEMP<=FRE1;
else if(CTR==4&&Code_in==0)
FM_TEMP<=FRE2;
else if(CTR==5)
FM_TEMP<=32'd286361;
else
WCK<=0;
// Count1<=6;
end
7'd12:begin
RST<=0;
// Count1<=13;
end
7'd15:begin
if(CTR==5&&Code_in==1)
Dout<=8'hc1;
else
Dout<=8'h41;
// Count1<=16;
end
7'd16:begin
WCK<=1;
// Count1<=17;
end
7'd17:begin
Dout<=FM_TEMP[31:24];//8'h00;//
WCK<=0;
// Count1<=18;
end
7'd18:begin
WCK<=1;
// Count1<=19;
end
7'd19:begin
Dout<=FM_TEMP[23:16];//8'h01;//
WCK<=0;
// Count1<=20;
end
7'd20:begin
WCK<=1;
// Count1<=21;
end
7'd21:begin
Dout<=FM_TEMP[15:8];//8'h01;//
WCK<=0;
// Count1<=22;
end
7'd22:begin
WCK<=1;
// Count1<=23;
end
7'd23:begin
Dout<=FM_TEMP[7:0];//8'h01;//
WCK<=0;
// Count1<=24;
end
7'd24:begin
WCK<=1;
// Count1<=25;
end
7'd25:begin
WCK<=0;
// Count1<=26;
end
7'd27:begin
FQD<=1;
// Count1<=27;
end
//5'd27:begin
// CTR<=0;
// end
7'd31:begin
FQD<=0;
// Count1<=2;
end
7'd199:begin
Count3<=0;
end
// default:Count1<=Count1+3'd1;
endcase
end
end
end
// end
endmodule
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