dac0832.v

来自「计算实用教程adadad9851实用教程」· Verilog 代码 · 共 22 行

module dac0832(
               data_in,
               wr,
               cs,
               data_out,
               WR_OUT,
               CS_OUT
               );
input [7:0] data_in;
input wr,cs;
output [7:0] data_out;
output WR_OUT,CS_OUT;

reg [7:0]data_out;
assign WR_OUT=wr;
assign CS_OUT=cs;
always@(data_in or wr or cs)
begin
    if((!wr)&&(!cs))
    data_out<=data_in;
end
endmodule