max542.v

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module max542(
                CLK,            //Clock of this module  8MHz
                Addr,           //0:write data to the low 8 bits;1:write data to the high 8 bits
				CS_in,          //Chip_select from the mcu to this module
				WR,             //Write signal from the mcu to this module
				D_in,           //Data input port from the mcu to this module
				CS,             //Chip_select to Max542
				SCLK,           //Serial clock to Max542
				D_out           //Data output port of this module and the data input port of Max542
              );

input CS_in;
input Addr;
input WR;
input CLK;
input [7:0] D_in;
output CS;
output SCLK;
output D_out;

reg[15:0] DATA;
reg[15:0] D_temp;
reg CS;
reg D_out;
reg SCLK;
reg[5:0] count;                   //state counter

wire CLK_4;

fp_2 fp_2_1(CLK,CLK_4);

always@(posedge CLK) 
	begin
		if((!CS_in)&(!WR)&(!Addr))
			D_temp[7:0]<=D_in;
		if((!CS_in)&(!WR)&Addr)
			D_temp[15:8]<=D_in;         
	end
	

always@(posedge CLK_4)
	begin
	    if(count<50)
			count<=count+1;
		else
		    count<=0;
	end 

always@(posedge CLK_4)
	   begin
		case(count)
			1:begin
				CS<=1;
				SCLK<=0;
				DATA<=D_temp;
			  end				
			3:begin
				CS<=0;
			  end
			4:begin
				D_out<=DATA[15];	
			  end
			5:begin
			    SCLK<=1;
			  end
			6:begin
				SCLK<=0;
				D_out<=DATA[14];
			  end
			7:begin
			    SCLK<=1;
			  end	
			8:begin
				SCLK<=0;
				D_out<=DATA[13];
			  end	
			9:begin
			    SCLK<=1;
			  end	
			10:begin
				SCLK<=0;
				D_out<=DATA[12];
			  end	
			11:begin
			    SCLK<=1;
			  end
			12:begin
				SCLK<=0;
				D_out<=DATA[11];
			  end
			13:begin
			    SCLK<=1;
			  end	
			14:begin
				SCLK<=0;
				D_out<=DATA[10];
			  end	
			15:begin
			    SCLK<=1;
			  end	
			16:begin
				SCLK<=0;
				D_out<=DATA[9];
			  end	
			17:begin
			    SCLK<=1;
			  end	
			18:begin
				SCLK<=0;
				D_out<=DATA[8];
			  end	
			19:begin
			    SCLK<=1;
			  end	
			20:begin
				SCLK<=0;
				D_out<=DATA[7];
			  end	
			21:begin
			    SCLK<=1;
			  end	
			22:begin
				SCLK<=0;
				D_out<=DATA[6];
			  end	
			23:begin
			    SCLK<=1;
			  end	
			24:begin
				SCLK<=0;
				D_out<=DATA[5];
			  end	
			25:begin
			    SCLK<=1;
			  end	
			26:begin
				SCLK<=0;
				D_out<=DATA[4];
			  end	
			27:begin
			    SCLK<=1;
			  end	
			28:begin
				SCLK<=0;
				D_out<=DATA[3];
			  end	
			29:begin
			    SCLK<=1;
			  end	
			30:begin
				SCLK<=0;
				D_out<=DATA[2];
			  end	
			31:begin
			    SCLK<=1;
			  end	
			32:begin
				SCLK<=0;
				D_out<=DATA[1];
			  end
			33:begin
			    SCLK<=1;
			  end	
			34:begin
				SCLK<=0;
				D_out<=DATA[0];
			  end	
			35:begin
				SCLK<=1;
			  end
			37:begin
				SCLK<=0;
			  end
			39:begin
				CS<=1;
			  end
		endcase   
	end	
	
endmodule