rom256addr.v

来自「计算实用教程adadad9851实用教程」· Verilog 代码 · 共 16 行

module ROM256ADDR(
					CLK,
					Aout
					);

input CLK;
output [7:0] Aout;

reg[7:0] Aout;

always@(posedge CLK)
	begin
		Aout<=Aout+1;
	end				
	
endmodule