ad9851_2007.map.eqn

计算实用教程adadad9851实用教程

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--D1_WCK is module_9851:inst2|WCK
--operation mode is normal

D1_WCK_lut_out = D1L329 & !D1L394 & (D1L407) # !D1L329 & (D1L325);
D1_WCK = DFFEAS(D1_WCK_lut_out, B1_Cout, VCC, , C1L2, , , , );


--D1_FQD is module_9851:inst2|FQD
--operation mode is normal

D1_FQD_lut_out = D1L331 # D1L336 & (D1L337 # D1L338);
D1_FQD = DFFEAS(D1_FQD_lut_out, B1_Cout, VCC, , C1L2, , , , );


--D1_RST is module_9851:inst2|RST
--operation mode is normal

D1_RST_lut_out = D1L317 & (D1L319 & (!D1_Count1[2]) # !D1L319 & D1_RST);
D1_RST = DFFEAS(D1_RST_lut_out, B1_Cout, VCC, , C1L2, , , , );


--K1_TIAOZHIBO is PSK_ASK:inst12|TIAOZHIBO
--operation mode is normal

K1_TIAOZHIBO_lut_out = D1L164 & K1_TIAOZHIBO # !D1L164 & (K1_code);
K1_TIAOZHIBO = DFFEAS(K1_TIAOZHIBO_lut_out, L1_Cout, VCC, , , , , , );


--C1L6 is ASIC74138:inst1|CSout[5]~74
--operation mode is normal

C1L6 = P2[5] # !P2[4] # !P2[7] # !P2[6];


--HB1_q_a[4] is ScanKey:inst29|altsyncram:reduce_or_rtl_0|altsyncram_d9l:auto_generated|q_a[4]
--RAM Block Operation Mode: ROM
--Port A Depth: 512, Port A Width: 1
--Port A Logical Depth: 512, Port A Logical Width: 5
--Port A Input: Registered, Port A Output: Un-registered
HB1_q_a[4]_PORT_A_address = BUS(T1_KR_temp[0], T1_KR_temp[1], T1_KR_temp[2], T1_KR_temp[3], T1_KR_temp[4], T1_KR_temp[5], T1_KC_temp[0], T1_KC_temp[1], T1_KC_temp[2]);
HB1_q_a[4]_PORT_A_address_reg = DFFE(HB1_q_a[4]_PORT_A_address, HB1_q_a[4]_clock_0, , , );
HB1_q_a[4]_clock_0 = ALE;
HB1_q_a[4]_PORT_A_data_out = MEMORY(, , HB1_q_a[4]_PORT_A_address_reg, , , , , , HB1_q_a[4]_clock_0, , , , , );
HB1_q_a[4] = HB1_q_a[4]_PORT_A_data_out[0];


--HB1_q_a[0] is ScanKey:inst29|altsyncram:reduce_or_rtl_0|altsyncram_d9l:auto_generated|q_a[0]
--RAM Block Operation Mode: ROM
--Port A Depth: 512, Port A Width: 1
--Port A Logical Depth: 512, Port A Logical Width: 5
--Port A Input: Registered, Port A Output: Un-registered
HB1_q_a[0]_PORT_A_address = BUS(T1_KR_temp[0], T1_KR_temp[1], T1_KR_temp[2], T1_KR_temp[3], T1_KR_temp[4], T1_KR_temp[5], T1_KC_temp[0], T1_KC_temp[1], T1_KC_temp[2]);
HB1_q_a[0]_PORT_A_address_reg = DFFE(HB1_q_a[0]_PORT_A_address, HB1_q_a[0]_clock_0, , , );
HB1_q_a[0]_clock_0 = ALE;
HB1_q_a[0]_PORT_A_data_out = MEMORY(, , HB1_q_a[0]_PORT_A_address_reg, , , , , , HB1_q_a[0]_clock_0, , , , , );
HB1_q_a[0] = HB1_q_a[0]_PORT_A_data_out[0];


--HB1_q_a[1] is ScanKey:inst29|altsyncram:reduce_or_rtl_0|altsyncram_d9l:auto_generated|q_a[1]
--RAM Block Operation Mode: ROM
--Port A Depth: 512, Port A Width: 1
--Port A Logical Depth: 512, Port A Logical Width: 5
--Port A Input: Registered, Port A Output: Un-registered
HB1_q_a[1]_PORT_A_address = BUS(T1_KR_temp[0], T1_KR_temp[1], T1_KR_temp[2], T1_KR_temp[3], T1_KR_temp[4], T1_KR_temp[5], T1_KC_temp[0], T1_KC_temp[1], T1_KC_temp[2]);
HB1_q_a[1]_PORT_A_address_reg = DFFE(HB1_q_a[1]_PORT_A_address, HB1_q_a[1]_clock_0, , , );
HB1_q_a[1]_clock_0 = ALE;
HB1_q_a[1]_PORT_A_data_out = MEMORY(, , HB1_q_a[1]_PORT_A_address_reg, , , , , , HB1_q_a[1]_clock_0, , , , , );
HB1_q_a[1] = HB1_q_a[1]_PORT_A_data_out[0];


--A1L124 is rtl~374
--operation mode is normal

A1L124 = HB1_q_a[0] & HB1_q_a[1];


--HB1_q_a[2] is ScanKey:inst29|altsyncram:reduce_or_rtl_0|altsyncram_d9l:auto_generated|q_a[2]
--RAM Block Operation Mode: ROM
--Port A Depth: 512, Port A Width: 1
--Port A Logical Depth: 512, Port A Logical Width: 5
--Port A Input: Registered, Port A Output: Un-registered
HB1_q_a[2]_PORT_A_address = BUS(T1_KR_temp[0], T1_KR_temp[1], T1_KR_temp[2], T1_KR_temp[3], T1_KR_temp[4], T1_KR_temp[5], T1_KC_temp[0], T1_KC_temp[1], T1_KC_temp[2]);
HB1_q_a[2]_PORT_A_address_reg = DFFE(HB1_q_a[2]_PORT_A_address, HB1_q_a[2]_clock_0, , , );
HB1_q_a[2]_clock_0 = ALE;
HB1_q_a[2]_PORT_A_data_out = MEMORY(, , HB1_q_a[2]_PORT_A_address_reg, , , , , , HB1_q_a[2]_clock_0, , , , , );
HB1_q_a[2] = HB1_q_a[2]_PORT_A_data_out[0];


--HB1_q_a[3] is ScanKey:inst29|altsyncram:reduce_or_rtl_0|altsyncram_d9l:auto_generated|q_a[3]
--RAM Block Operation Mode: ROM
--Port A Depth: 512, Port A Width: 1
--Port A Logical Depth: 512, Port A Logical Width: 5
--Port A Input: Registered, Port A Output: Un-registered
HB1_q_a[3]_PORT_A_address = BUS(T1_KR_temp[0], T1_KR_temp[1], T1_KR_temp[2], T1_KR_temp[3], T1_KR_temp[4], T1_KR_temp[5], T1_KC_temp[0], T1_KC_temp[1], T1_KC_temp[2]);
HB1_q_a[3]_PORT_A_address_reg = DFFE(HB1_q_a[3]_PORT_A_address, HB1_q_a[3]_clock_0, , , );
HB1_q_a[3]_clock_0 = ALE;
HB1_q_a[3]_PORT_A_data_out = MEMORY(, , HB1_q_a[3]_PORT_A_address_reg, , , , , , HB1_q_a[3]_clock_0, , , , , );
HB1_q_a[3] = HB1_q_a[3]_PORT_A_data_out[0];


--A1L118 is rtl~0
--operation mode is normal

A1L118 = HB1_q_a[4] & A1L124 & HB1_q_a[2] & HB1_q_a[3];


--C1L3 is ASIC74138:inst1|CSout[3]~75
--operation mode is normal

C1L3 = P2[6] # !P2[4] # !P2[7] # !P2[5];


--R1_COV is max195:inst21|COV
--operation mode is normal

R1_COV_lut_out = R1L62 & (R1L63 & R1_count[1] # !R1L63 & (R1_COV)) # !R1L62 & (R1_COV);
R1_COV = DFFEAS(R1_COV_lut_out, B4_Cout, VCC, , , , , , );


--R1_CLK_MAX195 is max195:inst21|CLK_MAX195
--operation mode is normal

R1_CLK_MAX195_lut_out = R1_count[1];
R1_CLK_MAX195 = DFFEAS(R1_CLK_MAX195_lut_out, B4_Cout, VCC, , , , , , );


--V1_CS is max542:inst31|CS
--operation mode is normal

V1_CS_lut_out = V1L45 & (V1_count[2] # !V1_count[1]) # !V1L45 & (V1_CS);
V1_CS = DFFEAS(V1_CS_lut_out, B4_Cout, VCC, , , , , , );


--V1_SCLK is max542:inst31|SCLK
--operation mode is normal

V1_SCLK_lut_out = V1_count[0] & (V1L50 & (V1L52) # !V1L50 & V1L46) # !V1_count[0] & (V1L50);
V1_SCLK = DFFEAS(V1_SCLK_lut_out, B4_Cout, VCC, , , , , , );


--V1_D_out is max542:inst31|D_out
--operation mode is normal

V1_D_out_lut_out = V1_count[0] & V1_D_out # !V1_count[0] & (V1L21 # V1_D_out & V1L22);
V1_D_out = DFFEAS(V1_D_out_lut_out, B4_Cout, VCC, , , , , , );


--R1_INT is max195:inst21|INT
--operation mode is normal

R1_INT_lut_out = R1L61 & (R1_count[3] & (R1_INT # R1_count[1]) # !R1_count[3] & (!R1_count[1])) # !R1L61 & R1_INT;
R1_INT = DFFEAS(R1_INT_lut_out, B4_Cout, VCC, , , , , , );


--GB1_q_a[7] is lpm_rom1:inst17|altsyncram:altsyncram_component|altsyncram_qbs:auto_generated|q_a[7]
--RAM Block Operation Mode: ROM
--Port A Depth: 4096, Port A Width: 1
--Port A Logical Depth: 4096, Port A Logical Width: 8
--Port A Input: Registered, Port A Output: Registered
GB1_q_a[7]_PORT_A_address = BUS(M1_ACC[20], M1_ACC[21], M1_ACC[22], M1_ACC[23], M1_ACC[24], M1_ACC[25], M1_ACC[26], M1_ACC[27], M1_ACC[28], M1_ACC[29], M1_ACC[30], M1_ACC[31]);
GB1_q_a[7]_PORT_A_address_reg = DFFE(GB1_q_a[7]_PORT_A_address, GB1_q_a[7]_clock_0, , , );
GB1_q_a[7]_clock_0 = CLK;
GB1_q_a[7]_PORT_A_data_out = MEMORY(, , GB1_q_a[7]_PORT_A_address_reg, , , , , , GB1_q_a[7]_clock_0, , , , , );
GB1_q_a[7]_PORT_A_data_out_reg = DFFE(GB1_q_a[7]_PORT_A_data_out, GB1_q_a[7]_clock_0, , , );
GB1_q_a[7] = GB1_q_a[7]_PORT_A_data_out_reg[0];


--GB1_q_a[6] is lpm_rom1:inst17|altsyncram:altsyncram_component|altsyncram_qbs:auto_generated|q_a[6]
--RAM Block Operation Mode: ROM
--Port A Depth: 4096, Port A Width: 1
--Port A Logical Depth: 4096, Port A Logical Width: 8
--Port A Input: Registered, Port A Output: Registered
GB1_q_a[6]_PORT_A_address = BUS(M1_ACC[20], M1_ACC[21], M1_ACC[22], M1_ACC[23], M1_ACC[24], M1_ACC[25], M1_ACC[26], M1_ACC[27], M1_ACC[28], M1_ACC[29], M1_ACC[30], M1_ACC[31]);
GB1_q_a[6]_PORT_A_address_reg = DFFE(GB1_q_a[6]_PORT_A_address, GB1_q_a[6]_clock_0, , , );
GB1_q_a[6]_clock_0 = CLK;
GB1_q_a[6]_PORT_A_data_out = MEMORY(, , GB1_q_a[6]_PORT_A_address_reg, , , , , , GB1_q_a[6]_clock_0, , , , , );
GB1_q_a[6]_PORT_A_data_out_reg = DFFE(GB1_q_a[6]_PORT_A_data_out, GB1_q_a[6]_clock_0, , , );
GB1_q_a[6] = GB1_q_a[6]_PORT_A_data_out_reg[0];


--GB1_q_a[5] is lpm_rom1:inst17|altsyncram:altsyncram_component|altsyncram_qbs:auto_generated|q_a[5]
--RAM Block Operation Mode: ROM
--Port A Depth: 4096, Port A Width: 1
--Port A Logical Depth: 4096, Port A Logical Width: 8
--Port A Input: Registered, Port A Output: Registered
GB1_q_a[5]_PORT_A_address = BUS(M1_ACC[20], M1_ACC[21], M1_ACC[22], M1_ACC[23], M1_ACC[24], M1_ACC[25], M1_ACC[26], M1_ACC[27], M1_ACC[28], M1_ACC[29], M1_ACC[30], M1_ACC[31]);
GB1_q_a[5]_PORT_A_address_reg = DFFE(GB1_q_a[5]_PORT_A_address, GB1_q_a[5]_clock_0, , , );
GB1_q_a[5]_clock_0 = CLK;
GB1_q_a[5]_PORT_A_data_out = MEMORY(, , GB1_q_a[5]_PORT_A_address_reg, , , , , , GB1_q_a[5]_clock_0, , , , , );
GB1_q_a[5]_PORT_A_data_out_reg = DFFE(GB1_q_a[5]_PORT_A_data_out, GB1_q_a[5]_clock_0, , , );
GB1_q_a[5] = GB1_q_a[5]_PORT_A_data_out_reg[0];


--GB1_q_a[4] is lpm_rom1:inst17|altsyncram:altsyncram_component|altsyncram_qbs:auto_generated|q_a[4]
--RAM Block Operation Mode: ROM
--Port A Depth: 4096, Port A Width: 1
--Port A Logical Depth: 4096, Port A Logical Width: 8
--Port A Input: Registered, Port A Output: Registered
GB1_q_a[4]_PORT_A_address = BUS(M1_ACC[20], M1_ACC[21], M1_ACC[22], M1_ACC[23], M1_ACC[24], M1_ACC[25], M1_ACC[26], M1_ACC[27], M1_ACC[28], M1_ACC[29], M1_ACC[30], M1_ACC[31]);
GB1_q_a[4]_PORT_A_address_reg = DFFE(GB1_q_a[4]_PORT_A_address, GB1_q_a[4]_clock_0, , , );
GB1_q_a[4]_clock_0 = CLK;
GB1_q_a[4]_PORT_A_data_out = MEMORY(, , GB1_q_a[4]_PORT_A_address_reg, , , , , , GB1_q_a[4]_clock_0, , , , , );
GB1_q_a[4]_PORT_A_data_out_reg = DFFE(GB1_q_a[4]_PORT_A_data_out, GB1_q_a[4]_clock_0, , , );
GB1_q_a[4] = GB1_q_a[4]_PORT_A_data_out_reg[0];


--GB1_q_a[3] is lpm_rom1:inst17|altsyncram:altsyncram_component|altsyncram_qbs:auto_generated|q_a[3]
--RAM Block Operation Mode: ROM
--Port A Depth: 4096, Port A Width: 1
--Port A Logical Depth: 4096, Port A Logical Width: 8
--Port A Input: Registered, Port A Output: Registered
GB1_q_a[3]_PORT_A_address = BUS(M1_ACC[20], M1_ACC[21], M1_ACC[22], M1_ACC[23], M1_ACC[24], M1_ACC[25], M1_ACC[26], M1_ACC[27], M1_ACC[28], M1_ACC[29], M1_ACC[30], M1_ACC[31]);
GB1_q_a[3]_PORT_A_address_reg = DFFE(GB1_q_a[3]_PORT_A_address, GB1_q_a[3]_clock_0, , , );
GB1_q_a[3]_clock_0 = CLK;
GB1_q_a[3]_PORT_A_data_out = MEMORY(, , GB1_q_a[3]_PORT_A_address_reg, , , , , , GB1_q_a[3]_clock_0, , , , , );
GB1_q_a[3]_PORT_A_data_out_reg = DFFE(GB1_q_a[3]_PORT_A_data_out, GB1_q_a[3]_clock_0, , , );
GB1_q_a[3] = GB1_q_a[3]_PORT_A_data_out_reg[0];


--GB1_q_a[2] is lpm_rom1:inst17|altsyncram:altsyncram_component|altsyncram_qbs:auto_generated|q_a[2]
--RAM Block Operation Mode: ROM
--Port A Depth: 4096, Port A Width: 1
--Port A Logical Depth: 4096, Port A Logical Width: 8
--Port A Input: Registered, Port A Output: Registered
GB1_q_a[2]_PORT_A_address = BUS(M1_ACC[20], M1_ACC[21], M1_ACC[22], M1_ACC[23], M1_ACC[24], M1_ACC[25], M1_ACC[26], M1_ACC[27], M1_ACC[28], M1_ACC[29], M1_ACC[30], M1_ACC[31]);
GB1_q_a[2]_PORT_A_address_reg = DFFE(GB1_q_a[2]_PORT_A_address, GB1_q_a[2]_clock_0, , , );
GB1_q_a[2]_clock_0 = CLK;
GB1_q_a[2]_PORT_A_data_out = MEMORY(, , GB1_q_a[2]_PORT_A_address_reg, , , , , , GB1_q_a[2]_clock_0, , , , , );
GB1_q_a[2]_PORT_A_data_out_reg = DFFE(GB1_q_a[2]_PORT_A_data_out, GB1_q_a[2]_clock_0, , , );
GB1_q_a[2] = GB1_q_a[2]_PORT_A_data_out_reg[0];


--GB1_q_a[1] is lpm_rom1:inst17|altsyncram:altsyncram_component|altsyncram_qbs:auto_generated|q_a[1]
--RAM Block Operation Mode: ROM
--Port A Depth: 4096, Port A Width: 1
--Port A Logical Depth: 4096, Port A Logical Width: 8
--Port A Input: Registered, Port A Output: Registered
GB1_q_a[1]_PORT_A_address = BUS(M1_ACC[20], M1_ACC[21], M1_ACC[22], M1_ACC[23], M1_ACC[24], M1_ACC[25], M1_ACC[26], M1_ACC[27], M1_ACC[28], M1_ACC[29], M1_ACC[30], M1_ACC[31]);
GB1_q_a[1]_PORT_A_address_reg = DFFE(GB1_q_a[1]_PORT_A_address, GB1_q_a[1]_clock_0, , , );
GB1_q_a[1]_clock_0 = CLK;
GB1_q_a[1]_PORT_A_data_out = MEMORY(, , GB1_q_a[1]_PORT_A_address_reg, , , , , , GB1_q_a[1]_clock_0, , , , , );
GB1_q_a[1]_PORT_A_data_out_reg = DFFE(GB1_q_a[1]_PORT_A_data_out, GB1_q_a[1]_clock_0, , , );
GB1_q_a[1] = GB1_q_a[1]_PORT_A_data_out_reg[0];


--GB1_q_a[0] is lpm_rom1:inst17|altsyncram:altsyncram_component|altsyncram_qbs:auto_generated|q_a[0]
--RAM Block Operation Mode: ROM
--Port A Depth: 4096, Port A Width: 1
--Port A Logical Depth: 4096, Port A Logical Width: 8
--Port A Input: Registered, Port A Output: Registered
GB1_q_a[0]_PORT_A_address = BUS(M1_ACC[20], M1_ACC[21], M1_ACC[22], M1_ACC[23], M1_ACC[24], M1_ACC[25], M1_ACC[26], M1_ACC[27], M1_ACC[28], M1_ACC[29], M1_ACC[30], M1_ACC[31]);
GB1_q_a[0]_PORT_A_address_reg = DFFE(GB1_q_a[0]_PORT_A_address, GB1_q_a[0]_clock_0, , , );
GB1_q_a[0]_clock_0 = CLK;
GB1_q_a[0]_PORT_A_data_out = MEMORY(, , GB1_q_a[0]_PORT_A_address_reg, , , , , , GB1_q_a[0]_clock_0, , , , , );
GB1_q_a[0]_PORT_A_data_out_reg = DFFE(GB1_q_a[0]_PORT_A_data_out, GB1_q_a[0]_clock_0, , , );
GB1_q_a[0] = GB1_q_a[0]_PORT_A_data_out_reg[0];


--D1_Dout[7] is module_9851:inst2|Dout[7]
--operation mode is normal

D1_Dout[7]_lut_out = D1L349 & (D1L348 # D1L344 & D1L350) # !D1L349 & D1L344;
D1_Dout[7] = DFFEAS(D1_Dout[7]_lut_out, B1_Cout, VCC, , C1L2, , , , );


--D1_Dout[6] is module_9851:inst2|Dout[6]
--operation mode is normal

D1_Dout[6]_lut_out = D1L68 & (D1L356 & !D1_Count1[3]) # !D1L68 & D1L354;
D1_Dout[6] = DFFEAS(D1_Dout[6]_lut_out, B1_Cout, VCC, , D1L79, , , , );


--D1_Dout[5] is module_9851:inst2|Dout[5]
--operation mode is normal

D1_Dout[5]_lut_out = D1L68 & (D1L361 & !D1_Count1[3]) # !D1L68 & D1L359;
D1_Dout[5] = DFFEAS(D1_Dout[5]_lut_out, B1_Cout, VCC, , D1L79, , , , );


--D1_Dout[4] is module_9851:inst2|Dout[4]
--operation mode is normal

D1_Dout[4]_lut_out = D1L68 & (D1L366 & !D1_Count1[3]) # !D1L68 & D1L364;
D1_Dout[4] = DFFEAS(D1_Dout[4]_lut_out, B1_Cout, VCC, , D1L79, , , , );


--D1_Dout[3] is module_9851:inst2|Dout[3]
--operation mode is normal

D1_Dout[3]_lut_out = D1L68 & (D1L371 & !D1_Count1[3]) # !D1L68 & D1L369;
D1_Dout[3] = DFFEAS(D1_Dout[3]_lut_out, B1_Cout, VCC, , D1L79, , , , );


--D1_Dout[2] is module_9851:inst2|Dout[2]
--operation mode is normal

D1_Dout[2]_lut_out = D1L68 & (D1L376 & !D1_Count1[3]) # !D1L68 & D1L374;
D1_Dout[2] = DFFEAS(D1_Dout[2]_lut_out, B1_Cout, VCC, , D1L79, , , , );


--D1_Dout[1] is module_9851:inst2|Dout[1]
--operation mode is normal

D1_Dout[1]_lut_out = D1L68 & (D1L381 & !D1_Count1[3]) # !D1L68 & D1L379;
D1_Dout[1] = DFFEAS(D1_Dout[1]_lut_out, B1_Cout, VCC, , D1L79, , , , );


--D1_Dout[0] is module_9851:inst2|Dout[0]
--operation mode is normal

D1_Dout[0]_lut_out = D1L68 & (D1_Count1[3] # D1L386) # !D1L68 & D1L384;
D1_Dout[0] = DFFEAS(D1_Dout[0]_lut_out, B1_Cout, VCC, , D1L79, , , , );


--D1L394 is module_9851:inst2|add~2005
--operation mode is arithmetic

D1L394 = D1_Count3[0] $ !D1L164;

--D1L395 is module_9851:inst2|add~2007
--operation mode is arithmetic

D1L395 = CARRY(D1_Count3[0] & !D1L164);


--D1L396 is module_9851:inst2|add~2010
--operation mode is arithmetic

D1L396_carry_eqn = D1L402;
D1L396 = D1_Count2[4] $ (!D1L396_carry_eqn);

--D1L397 is module_9851:inst2|add~2012
--operation mode is arithmetic

D1L397 = CARRY(D1_Count2[4] & (!D1L402));


--D1L398 is module_9851:inst2|add~2015
--operation mode is normal

D1L398_carry_eqn = D1L397;
D1L398 = D1_Count2[5] $ (D1L398_carry_eqn);


--D1L399 is module_9851:inst2|add~2020
--operation mode is arithmetic

D1L399 = A1L125 $ D1_Count2[0];

--D1L400 is module_9851:inst2|add~2022
--operation mode is arithmetic

D1L400 = CARRY(A1L125 & D1_Count2[0]);


--D1L37 is module_9851:inst2|Decoder~1644
--operation mode is normal

D1L37 = !D1L398 & !D1L399;


--D1L401 is module_9851:inst2|add~2025
--operation mode is arithmetic

D1L401_carry_eqn = D1L406;
D1L401 = D1_Count2[3] $ (D1L401_carry_eqn);

--D1L402 is module_9851:inst2|add~2027
--operation mode is arithmetic

D1L402 = CARRY(!D1L406 # !D1_Count2[3]);


--D1L403 is module_9851:inst2|add~2030
--operation mode is arithmetic

D1L403_carry_eqn = D1L400;
D1L403 = D1_Count2[1] $ (D1L403_carry_eqn);

--D1L404 is module_9851:inst2|add~2032
--operation mode is arithmetic

D1L404 = CARRY(!D1L400 # !D1_Count2[1]);


--D1L405 is module_9851:inst2|add~2035
--operation mode is arithmetic

D1L405_carry_eqn = D1L404;
D1L405 = D1_Count2[2] $ (!D1L405_carry_eqn);

--D1L406 is module_9851:inst2|add~2037
--operation mode is arithmetic

D1L406 = CARRY(D1_Count2[2] & (!D1L404));


--D1L320 is module_9851:inst2|Select~4788
--operation mode is normal

D1L320 = D1L403 # D1L405;


--D1L321 is module_9851:inst2|Select~4789
--operation mode is normal

D1L321 = D1L396 & D1L37 & (!D1L320 # !D1L401);


--D1L322 is module_9851:inst2|Select~4790
--operation mode is normal

D1L322 = !D1L403 & !D1L405 & !D1L401 & !D1L399;


--D1L323 is module_9851:inst2|Select~4791
--operation mode is normal

D1L323 = D1L401 & D1L396;


--D1L324 is module_9851:inst2|Select~4792
--operation mode is normal

D1L324 = D1L398 # D1L388 # !D1L396 & !D1L322;


--D1_Count1[4] is module_9851:inst2|Count1[4]
--operation mode is arithmetic

D1_Count1[4]_carry_eqn = D1L16;
D1_Count1[4]_lut_out = D1_Count1[4] $ (!D1_Count1[4]_carry_eqn);
D1_Count1[4] = DFFEAS(D1_Count1[4]_lut_out, B1_Cout, VCC, , C1L2, , , A1L119, );