max195.v

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module max195(
				COV,             //Starting of conversion for Max195
				CS,              //Chip_select of this module
				RD,              //RD signal from mcu
				Addr,            //0:low 8 bits of data; 1:high 8 bits of data 
				D_out,           //Data output port to mcu
				D_in,            //Data input port from Max195
				CLK,             //Clock of this module ,8 times of the clock for ADC Max195  8MHz
				INT,             //Interrupt signal to mcu
				CLK_MAX195       //1MHz
              );

output COV;
input CS;
input RD;
input D_in;
input CLK;
input Addr;
output [7:0] D_out;
output INT;
output CLK_MAX195;

reg[15:0] DATA;
reg[15:0] D_temp;
reg[7:0] D_out;
reg INT;
reg[6:0] count;                   //Status Counter for this module
reg CLK_MAX195;
reg COV;

wire CLK_4;

fp_2 fp_2_1(CLK,CLK_4);

always@(posedge CLK_4)
	begin
		count<=count+1;
		if(count[1])
		  CLK_MAX195<=1;
		else
		  CLK_MAX195<=0; 
	end
	
	
always@(posedge CLK_4)
	begin
		case(count)
			1:begin
			    INT<=1;
				COV<=0;
			  end
			7:COV<=1;
			9:DATA[15]<=D_in;
			13:DATA[14]<=D_in;
			17:DATA[13]<=D_in;
			21:DATA[12]<=D_in;
			25:DATA[11]<=D_in;
			29:DATA[10]<=D_in;
			33:DATA[9]<=D_in;
			37:DATA[8]<=D_in;
			41:DATA[7]<=D_in;
			45:DATA[6]<=D_in;
			49:DATA[5]<=D_in;
			53:DATA[4]<=D_in;
			57:DATA[3]<=D_in;
			61:DATA[2]<=D_in;
			65:DATA[1]<=D_in;
			69:DATA[0]<=D_in;
			71:INT<=0;
			79:INT<=1;
			80:D_temp<=DATA;
		endcase	
	end	


always@(posedge CLK)
	begin
		if((!CS)&(!RD)&(!Addr))
		  D_out<=D_temp[7:0];
		if((!CS)&(!RD)&Addr)
		  D_out<=D_temp[15:8];
	end
	
endmodule