fp_5.v

来自「计算实用教程adadad9851实用教程」· Verilog 代码 · 共 18 行

module fp_5(CLK_in,CLK_out);
 
input CLK_in;
output CLK_out;

reg [2:0] Cout;

assign CLK_out=Cout[2];

always @( posedge CLK_in)
  begin
    if(Cout<4)
      Cout<=Cout+1;
    else
      Cout<=0;   
  end
endmodule