psk_ask.v

来自「计算实用教程adadad9851实用教程」· Verilog 代码 · 共 48 行

module PSK_ASK(
				CTR,
				CLK,
				TIAOZHIBO,
				CODEout
				);
				
input CTR;					//Contrl signal from P1.x,1:ASK,0:PSK
input CLK;					//Main CLK    10KHz
output TIAOZHIBO;			
output CODEout;	

reg TIAOZHIBO;
reg[2:0] count;
reg code;
reg AD7501A0;

assign CODEout=code;

always@(posedge CLK)
	begin
		count<=count+1;
	end
	
always@(posedge CLK)
	begin
		case(count)
		0:code<=0;
		1:code<=1;
		2:code<=0;
		3:code<=1;
		4:code<=0;
		5:code<=1;
		6:code<=0;
		7:code<=1;
			
		endcase
		if(CTR)				//PSK            AD7501: IN0:Signal,IN1:nSingnal,IN2:GND
			begin
				if(!code)
					TIAOZHIBO<=0;
				else
					TIAOZHIBO<=1;	
			end
		
	end	
	
endmodule