hd66773.txt

TFT LCD HD66773 INITIAL CODE

void HD66773_INIT(void)
{
	if(HD66773_data_bus==0)
	{set_reg8();}
  HD66773_REG(0x0000,0x0001) ; //osc start
	Delay1(50);
	HD66773_REG(0x0001,0x0113) ;//driver output control 0x0213 for PV
	Delay1(50);
	HD66773_REG(0x0002,0x0700) ; //lcd drive ac control
	Delay1(50);
	HD66773_REG(0x0005,0x1030 ) ;// entry mode
	Delay1(50);
  HD66773_REG(0x0006,0x0000 ) ;//compare register
	Delay1(50);
  HD66773_REG(0x0007,0x0004 ) ;//display control
	Delay1(50);
	HD66773_REG(0x000B,0x1004 ) ;//frame cycle control
	Delay1(50);
	HD66773_REG(0x000C,0x0005 ) ;//power control 3
	Delay1(50);
	HD66773_REG(0x000D,0x0401 ) ;//power control 4
  Delay1(50);
  HD66773_REG(0x000E,0x0D18 ) ; //power control 5
  Delay1(50);
	HD66773_REG(0x0003,0x0214 ) ; //power control 1
	Delay1(50);
	HD66773_REG(0x0004,0x8000 ) ;//power control 2
  Delay1(50);
	HD66773_REG(0x000E,0x2910 ) ;//power control 5
	Delay1(50);
	HD66773_REG(0x000D,0x0512 ) ;//power control 4
  Delay1(50);
	HD66773_REG(0x0021,0x0000 ) ;//ram address set 0x0002 for PV panel
	Delay1(50);
	HD66773_REG(0x0030,0x0000 ) ;
	HD66773_REG(0x0031,0x0000 ) ;
	HD66773_REG(0x0032,0x0000 ) ;
	HD66773_REG(0x0033,0x0000 ) ;
	HD66773_REG(0x0034,0x0000 ) ;
	HD66773_REG(0x0035,0x0707 ) ;
	HD66773_REG(0x0036,0x0707 ) ;
	HD66773_REG(0x0037,0x0000 ) ;
  Delay1(50);
	HD66773_REG(0x000F,0x0000 ) ;//gate scan start 
  Delay1(50);
	HD66773_REG(0x0011,0x0000 ) ;
  Delay1(50);
	//SCRNDRPOS
	HD66773_REG(0x0014,0x9F00 ) ;//0x9F00
  Delay1(50);
	//SCRNDRPOS2
	HD66773_REG(0x0015,0x9F00 ) ;//0x9F00
	Delay1(50);
	//HRAMADDRPOS
	HD66773_REG(0x0016,0x7F00 ) ;
	Delay1(50);
	//VRAMADDRPOS
	HD66773_REG(0x0017,0x9F00 ) ;
	Delay1(50);
	HD66773_REG(0x003A,0x0000 ) ;
	HD66773_REG(0x003B,0x0000 ) ;
	Delay1(50);
	//DISCON1
	HD66773_REG(0x0007,0x0005 ) ;//
  Delay1(50);
	//DISCON2
	HD66773_REG(0x0007,0x0025 ) ;//
	Delay1(50);
	//DISCON3
  HD66773_REG(0x0007,0x0027 ) ;//
	Delay1(50);
	//DISCON4
	HD66773_REG(0x0007,0x0037 ) ;//display on
	Delay1(50);
	}