📄 addr.s
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;===================================================================
; Addr.s
;===================================================================
gbll __BIG_ENDIAN
__BIG_ENDIAN setl {false}
; Pre-defined constants
USERMODE EQU 0x10
FIQMODE EQU 0x11
IRQMODE EQU 0x12
SVCMODE EQU 0x13
ABORTMODE EQU 0x17
UNDEFMODE EQU 0x1b
MODEMASK EQU 0x1f
NOINT EQU 0xc0
; Memory control
BWSCON equ 0x48000000 ; Bus width & wait status
BANKCON0 equ 0x48000004 ; Boot ROM control
BANKCON1 equ 0x48000008 ; BANK1 control
BANKCON2 equ 0x4800000c ; BANK2 cControl
BANKCON3 equ 0x48000010 ; BANK3 control
BANKCON4 equ 0x48000014 ; BANK4 control
BANKCON5 equ 0x48000018 ; BANK5 control
BANKCON6 equ 0x4800001c ; BANK6 control
BANKCON7 equ 0x48000020 ; BANK7 control
REFRESH equ 0x48000024 ; DRAM/SDRAM refresh
BANKSIZE equ 0x48000028 ; Flexible Bank Size
MRSRB6 equ 0x4800002c ; Mode register set for SDRAM
MRSRB7 equ 0x48000030 ; Mode register set for SDRAM
; Interrupt control register
SRCPND equ 0x4A000000 ; Interrupt source pending status
INTMOD equ 0x4A000004 ; Interrupt mode control
INTMSK equ 0x4A000008 ; Interrupt mask control
PRIORITY equ 0x4A00000C ; Interrupt request priority control
INTPND equ 0x4A000010 ; Interrupt request status
INTOFFSET equ 0x4A000014 ; Interruot request source offset
SUBSRCPND equ 0x4A000018 ; Interrupt sub source pending status
INTSUBMSK equ 0x4A00001C ; Interrupt sub mask control
BIT_EINT0 equ (0x1) ; Interrupt Pending bits define
BIT_EINT1 equ (0x1<<1) ;
BIT_EINT2 equ (0x1<<2) ;
BIT_EINT3 equ (0x1<<3) ;
BIT_EINT4_7 equ (0x1<<4) ;
BIT_EINT8_23 equ (0x1<<5) ;
BIT_NOTUSED6 equ (0x1<<6) ;
BIT_BAT_FLT equ (0x1<<7) ;
BIT_TICK equ (0x1<<8) ;
BIT_WDT equ (0x1<<9) ;
BIT_TIMER0 equ (0x1<<10) ;
BIT_TIMER1 equ (0x1<<11) ;
BIT_TIMER2 equ (0x1<<12) ;
BIT_TIMER3 equ (0x1<<13) ;
BIT_TIMER4 equ (0x1<<14) ;
BIT_UART2 equ (0x1<<15) ;
BIT_LCD equ (0x1<<16) ;
BIT_DMA0 equ (0x1<<17) ;
BIT_DMA1 equ (0x1<<18) ;
BIT_DMA2 equ (0x1<<19) ;
BIT_DMA3 equ (0x1<<20) ;
BIT_SDI equ (0x1<<21) ;
BIT_SPI0 equ (0x1<<22) ;
BIT_UART1 equ (0x1<<23) ;
BIT_NOTUSED24 equ (0x1<<24) ;
BIT_USBD equ (0x1<<25) ;
BIT_USBH equ (0x1<<26) ;
BIT_IIC equ (0x1<<27) ;
BIT_UART0 equ (0x1<<28) ;
BIT_SPI1 equ (0x1<<29) ;
BIT_RTC equ (0x1<<30) ;
BIT_ADC equ (0x1<<31) ;
BIT_ALLMSK equ (0xFFFFFFFF) ;
BIT_SUB_ALLMSK equ (0x7FF) ;
BIT_SUB_ADC equ (0x1<<10) ;
BIT_SUB_TC equ (0x1<<9) ;
BIT_SUB_ERR2 equ (0x1<<8) ;
BIT_SUB_TXD2 equ (0x1<<7) ;
BIT_SUB_RXD2 equ (0x1<<6) ;
BIT_SUB_ERR1 equ (0x1<<5) ;
BIT_SUB_TXD1 equ (0x1<<4) ;
BIT_SUB_RXD1 equ (0x1<<3) ;
BIT_SUB_ERR0 equ (0x1<<2) ;
BIT_SUB_TXD0 equ (0x1<<1) ;
BIT_SUB_RXD0 equ (0x1<<0) ;
; Clock control register
LOCKTIME equ 0x4C000000 ; PLL lock time counter
MPLLCON equ 0x4C000004 ; MPLL control
UPLLCON equ 0x4C000008 ; UPLL control
CLKCON equ 0x4C00000C ; Clock generator control
CLKSLOW equ 0x4c000010 ; Slow clock control
CLKDIVN equ 0x4C000014 ; Clock divider control
; Uart register
ULCON0 equ 0x50000000 ; UART 0 Line control
UCON0 equ 0x50000004 ; UART 0 Control
UFCON0 equ 0x50000008 ; UART 0 FIFO control
UMCON0 equ 0x5000000C ; UART 0 Modem control
UTRSTAT0 equ 0x50000010 ; UART 0 Tx/Rx status
UERSTAT0 equ 0x50000014 ; UART 0 RX error status
UFSTAT0 equ 0x50000018 ; UART 0 FIFO status
UMSTAT0 equ 0x5000001C ; UART 0 Modem status
UBRDIV0 equ 0x50000028 ; UART 0 Baud rate divisor
ULCON1 equ 0x50004000 ; UART 1 Line control
UCON1 equ 0x50004004 ; UART 1 Control
UFCON1 equ 0x50004008 ; UART 1 FIFO control
UMCON1 equ 0x5000400C ; UART 1 Modem control
UTRSTAT1 equ 0x50004010 ; UART 1 Tx/Rx status
UERSTAT1 equ 0x50004014 ; UART 1 RX error status
UFSTAT1 equ 0x50004018 ; UART 1 FIFO status
UMSTAT1 equ 0x5000401C ; UART 1 Modem status
UBRDIV1 equ 0x50004028 ; UART 1 Baud rate divisor
ULCON2 equ 0x50008000 ; UART 2 Line control
UCON2 equ 0x50008004 ; UART 2 Control
UFCON2 equ 0x50008008 ; UART 2 FIFO control
UMCON2 equ 0x5000800C ; UART 2 Modem control
UTRSTAT2 equ 0x50008010 ; UART 2 Tx/Rx status
UERSTAT2 equ 0x50008014 ; UART 0 RX error status
UFSTAT2 equ 0x50008018 ; UART 2 FIFO status
UBRDIV2 equ 0x50008028 ; UART 2 Baud rate divisor
[ __BIG_ENDIAN ; Big endian
UTXH0 equ 0x50000023 ;UART 0 Transmission Hold
URXH0 equ 0x50000027 ;UART 0 Receive buffer
UTXH1 equ 0x50004023 ;UART 1 Transmission Hold
URXH1 equ 0x50004027 ;UART 1 Receive buffer
UTXH2 equ 0x50008023 ;UART 2 Transmission Hold
URXH2 equ 0x50008027 ;UART 2 Receive buffer
| ; Little endian
UTXH0 equ 0x50000020 ;UART 0 Transmission Hold
URXH0 equ 0x50000024 ;UART 0 Receive buffer
UTXH1 equ 0x50004020 ;UART 1 Transmission Hold
URXH1 equ 0x50004024 ;UART 1 Receive buffer
UTXH2 equ 0x50008020 ;UART 2 Transmission Hold
URXH2 equ 0x50008024 ;UART 2 Receive buffer
]
; Watch dog timer
WTCON equ 0x53000000 ;
; I/O Ports
GPACON equ 0x56000000 ; Port A control
GPADAT equ 0x56000004 ; Port A data
GPBCON equ 0x56000010 ; Port B control
GPBDAT equ 0x56000014 ; Port B data
GPBUP equ 0x56000018 ; Port B pull-up control
GPCCON equ 0x56000020 ; Port C control
GPCDAT equ 0x56000024 ; Port C data
GPCUP equ 0x56000028 ; Port C pull-up control
GPDCON equ 0x56000030 ; Port D control
GPDDAT equ 0x56000034 ; Port D data
GPDUP equ 0x56000038 ; Port D pull-up control
GPECON equ 0x56000040 ; Port E control
GPEDAT equ 0x56000044 ; Port E data
GPEUP equ 0x56000048 ; Port E pull-up control
GPFCON equ 0x56000050 ; Port F control
GPFDAT equ 0x56000054 ; Port F data
GPFUP equ 0x56000058 ; Port F pull-up control
GPGCON equ 0x56000060 ; Port G control
GPGDAT equ 0x56000064 ; Port G data
GPGUP equ 0x56000068 ; Port G pull-up control
GPHCON equ 0x56000070 ; Port H control
GPHDAT equ 0x56000074 ; Port H data
GPHUP equ 0x56000078 ; Port H pull-up control
MISCCR equ 0x56000080 ; Miscellaneous control
DCLKCON equ 0x56000084 ; DCLK0/1 control
EXTINT0 equ 0x56000088 ; External interrupts signaling methods register 0
EXTINT1 equ 0x5600008C ; External interrupts signaling methods register 1
EXTINT2 equ 0x56000090 ; External interrupts signaling methods register 2
EINTFLT0 equ 0x56000094 ; Reserved
EINTFLT1 equ 0x56000098 ; Reserved
EINTFLT2 equ 0x5600009C ; External interrupt filter control register 2
EINTFLT3 equ 0x560000A0 ; External interrupt filter control register 3
EINTMASK equ 0x560000A4 ; External interrupt mask
EINTPEND equ 0x560000A8 ; External interrupt pending
GSTATUS0 equ 0x560000AC ; External pin status
GSTATUS1 equ 0x560000B0 ; Chip ID(0x32410002)
GSTATUS2 equ 0x560000B4 ; Reset type
GSTATUS3 equ 0x560000B8 ; Saved data0(32-bit) before entering POWER_OFF mode
GSTATUS4 equ 0x560000BC ; Saved data0(32-bit) before entering POWER_OFF mode
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