📄 boot.s
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;===============================================================
; boot.s
;===============================================================
include MemoryConfig.s
include Addr.s
include Option.s
BPS_DATA equ ((PCLK/(115200 *16))-1)
MPLL_DATA equ ((0xA1<<12) | (0x3<<4) | 0x01)
import |Image$$BOOT$$Base|
import |Image$$BOOT$$Limit|
import |Image$$RO$$Base|
import |Image$$RO$$Limit|
import |Image$$RW$$Base|
import |Image$$RW$$Limit|
import |Image$$ZI$$Base|
import |Image$$ZI$$Limit|
import Main
import Test
import CopySelf
import Move_RORWZI_InSdram
macro
$HandleLabel SetHandle $HandeAddr
$HandleLabel
sub sp, sp, #4
stmfd sp!, {r0}
ldr r0, =$HandeAddr
ldr r0, [r0]
str r0, [sp, #4]
ldmfd sp!, {r0, pc}
mend
area Init, code, readonly
entry
b Reset
b Label_UndefHandle ;handle for undefined mode
b Label_SWIHandle ;handle for SWI interrupt
b Label_PabortHandle ;handle for PAbort
b Label_DabortHandle ;handle for DAbort
b . ;reserved
b Label_IRQHandler ;handle for IRQ interrupt
b Label_FIQHandler ;handle for FIQ interrupt
b .
b .
b .
b .
b .
Label_UndefHandle SetHandle Addr_UndefHandle
Label_SWIHandle SetHandle Addr_SWIHandle
Label_PabortHandle SetHandle Addr_HandlePabort
Label_DabortHandle SetHandle Addr_HandleDabort
Label_IRQHandler SetHandle Addr_HandleIRQ
Label_FIQHandler SetHandle Addr_HandleFIQ
Reset
;close watchdog timer
ldr r1, =WTCON
ldr r2, =0x0
str r2, [r1]
;disable all interrupts
ldr r1, =INTMSK
ldr r2, =0xFFFFFFFF
str r2, [r1]
;disable all sub interrupts
ldr r1, =INTSUBMSK
ldr r2, =0x7FF
str r2, [r1]
;set all interrupt as IRQ
ldr r1, =INTMOD
ldr r2, =0x0
str r2, [r1]
;set clk div FCLK:HCLK:PCLK 1:2:4
ldr r1, =CLKDIVN
ldr r2, =0x03
str r2, [r1]
; changing into AsyncBusMode because HDIVN = 1
mrc p15, 0x0, r1, c1, c0, 0
orr r1, r1, #0xC0000000
mcr p15, 0x0, r1, c1, c0, 0
;LOCKTIME
ldr r1, =LOCKTIME
ldr r2, =0x00FFFFFF
str r2, [r1]
;set UPLL at 48MHZ
ldr r1, =UPLLCON
ldr r2, =0x00040012
str r2, [r1]
;nop delay for set UPll, MPLL at the same time
nop
nop
nop
nop
nop
nop
nop
;set MPLL at 202.8M
ldr r1, =MPLLCON
ldr r2, =MPLL_DATA
str r2, [r1]
;delay for lock time
mov r1, #0x2000
1
subs r1, r1, #1
bne %b1
;Set memory control registers
SetMemoryRegisters
ldr r0, =SMRDATA
ldr r1, =BWSCON ;BWSCON Address
add r2, r0, #52 ;End address of SMRDATA
0
ldr r3, [r0], #4
str r3, [r1], #4
cmp r2, r0
bne %b0
;initialize all mode stacks
bl InitStacks
; initialize led4, led5 for debug
bl LEDINIT
;initialize uart0 for input/output
bl Uart0_Init_OnBoot
;Copy self to ram(SDRM)
bl CopySelf
;adjust position in the ram
bl Move_RORWZI_InSdram
;Setup IRQ handle
ldr r0, =Addr_HandleIRQ ;This routine is needed
ldr r1, =IsrIRQ ;if there isn't 'subs pc,lr,#4' at 0x18, 0x1c
str r1, [r0]
;Setup IRQ handle
ldr r0, =ADDR_HandleEINT0
ldr r1, =IrqHandler_EINT0
str r1, [r0]
; set up EINT0 interrupt for a test
; set bit0 of Port F for EINT0 fuction
ldr r0, =GPFCON
ldr r1, [r0]
bic r1, r1, #0x03
orr r1, r1, #0x02
str r1, [r0]
; set EINT0 Rising edge triggered
ldr r0, =EXTINT0
ldr r1, [r0]
bic r1, r1, #0x07
orr r1, r1, #0x04
str r1, [r0]
; enable
ldr r0, =INTMSK
ldr r1, [r0]
bic r1, r1, #0x03
str r1, [r0]
; clear pending register
ldr r0, =SRCPND
mov r1, #BIT_EINT0
str r1, [r0]
ldr r0, =INTPND
mov r1, #BIT_EINT0
str r1, [r0]
;clear I, F bit to enable IRQ, FIQ
mrs r0, cpsr;
bic r0, r0, #NOINT
msr cpsr_cxsf, r0
bl Main
b .
;===============================================================
;IsrIRQ
;===============================================================
IsrIRQ
sub sp, sp, #4
stmfd sp!, {r0-r1}
ldr r1, =INTOFFSET
ldr r1, [r1]
ldr r0, =ADDR_HandleEINT0
add r0, r0, r1, lsl #2
ldr r0, [r0]
str r0, [sp, #8]
ldmfd sp!, {r0-r1, pc}
;===============================================================
;Irq Handler
;===============================================================
IrqHandler_EINT0
stmfd sp!, {r0, r1, lr}
mov r0, sp
bl Uart0_SendAddr
ldr r0, [sp, #0x0C] ;saved data
bl Uart0_SendData
tst r0, #0x01
beq %f1
0
bl LED4_ON
mov r0, #0x00
b %f2
1
bl LED4_OFF
mov r0, #0x01
2
str r0, [sp, #0x0C]
ldr r0, =SRCPND
mov r1, #BIT_EINT0
str r1, [r0]
ldr r0, =INTPND
mov r1, #BIT_EINT0
str r1, [r0]
ldmfd sp!, {r0, r1, lr}
subs pc, lr, #4 ; IRQ return
;===============================================================
;function initializing stacks
;===============================================================
InitStacks
mrs r0, cpsr
bic r0, r0, #MODEMASK
orr r1, r0, #UNDEFMODE|NOINT
msr cpsr_cxsf, r1 ;UndefMode
ldr sp, =UndefStack
orr r1, r0, #ABORTMODE|NOINT
msr cpsr_cxsf, r1 ;AbortMode
ldr sp, =AbortStack
orr r1, r0, #IRQMODE|NOINT
msr cpsr_cxsf, r1 ;IRQMode
ldr sp, =IRQStack
; test data
mov r1, #0x0;
stmfd sp!, {r1};
orr r1, r0, #FIQMODE|NOINT
msr cpsr_cxsf, r1 ;FIQMode
ldr sp, =FIQStack
bic r0, r0, #MODEMASK|NOINT
orr r1, r0, #SVCMODE
msr cpsr_cxsf, r1 ;SVCMode
ldr sp, =SVCStack
;USER mode has not be initialized.
mov pc, lr
;The LR register won't be valid if the current mode is not SVC mode.
;========================================================================
;Uart0 fuctions, for input/output
;========================================================================
Uart0_Init_OnBoot
;initialize UART0 for input/ouput
stmfd sp!, {r1-r2}
ldr r1, =GPHCON ;open corresponding ports for Uart function
ldr r2, [r1]
bic r2, r2, #0xFF
orr r2, r2, #0xAA
str r2, [r1] ;enable the UART0 pins
ldr r1, =UFCON0
ldr r2, =0 ;diabale FIFO control
str r2, [r1]
ldr r1, =UMCON0
ldr r2, =0 ;diabale MODEM control
str r2, [r1]
ldr r1, =ULCON0
ldr r2, =0x03 ;Normal mode, No parity, One stop, 8-bit
str r2, [r1]
ldr r1, =UCON0
ldr r2, =0x005 ;
str r2, [r1]
ldr r1, =UBRDIV0
ldr r2, =BPS_DATA;set bps 115200, UBRDIVn=(int)(PCLK/(bps x 16))-1
str r2, [r1]
ldmfd sp!, {r1-r2}
mov pc, lr
export Uart0_GetByte
Uart0_GetByte
stmfd sp!, {r1}
ldr r1, =UTRSTAT0
0
ldr r0, [r1]
tst r0, #0x01
beq %b0
ldr r1, =URXH0
ldrb r0, [r1]
ldmfd sp!, {r1}
mov pc, lr
export Uart0_SendByte
Uart0_SendByte
stmfd sp!, {r0-r3}
ldr r2, =UTRSTAT0
0
ldr r1, [r2]
tst r1, #0x02
beq %b0
ldr r3, =0x10
1
subs r3, r3, #1
bne %b1
ldr r1, =UTXH0
strb r0, [r1]
ldmfd sp!, {r0-r3}
mov pc, lr
export Uart0_SendByteHex
Uart0_SendByteHex ;byte is in r0
stmfd sp!, {r0-r1, lr}
mov r1, r0
mov r0, r1, lsr #4
and r0, r0, #0x0F
cmp r0, #0x0A
add r0, r0, #0x30 ;add '0'
addcs r0, r0, #0x07 ;add 'A'-'9' -1
bl Uart0_SendByte
mov r0, r1
and r0, r0, #0x0F
cmp r0, #0x0A
add r0, r0, #0x30 ;add '0'
addcs r0, r0, #0x07 ;add 'A'-'9' -1
bl Uart0_SendByte
ldmfd sp!, {r0-r1, pc}
export Uart0_SendData
Uart0_SendData
stmfd sp!, {r0-r2, lr}
mov r1, r0
mov r2, #28;
0
mov r0, r1, lsr r2
and r0, r0, #0x0F
cmp r0, #0x0A
add r0, r0, #0x30 ;add '0'
addcs r0, r0, #0x07 ;add 'A'-'9' -1
bl Uart0_SendByte
subs r2, r2, #0x04
bpl %b0
ldmfd sp!, {r0-r2, pc}
export Uart0_SendAddr
Uart0_SendAddr ;addr is in r0
stmfd sp!, {r0-r2, lr}
mov r1, r0
mov r0, #0x30 ;output '0'
bl Uart0_SendByte
mov r0, #0x78 ;output 'x'
bl Uart0_SendByte
mov r2, #28;
0
mov r0, r1, lsr r2
and r0, r0, #0x0F
cmp r0, #0x0A
add r0, r0, #0x30 ;add '0'
addcs r0, r0, #0x07 ;add 'A'-'9' -1
bl Uart0_SendByte
subs r2, r2, #0x04
bpl %b0
mov r0, #0x3A ;output ':'
bl Uart0_SendByte
ldmfd sp!, {r0-r2, pc}
;===============================================================
;LED functions
;===============================================================
export LEDINIT
LEDINIT
; use Eint4, Eint5 as output pin to light the leds
stmfd sp!, {r1-r2}
ldr r1, =GPFCON
ldr r2, [r1]
bic r2, r2, #0x0F00
orr r2, r2, #0x0500
str r2, [r1]
ldr r1, =GPFUP
ldr r2, [r1]
bic r2, r2, #0x30
orr r2, r2, #0x30
str r2, [r1]
ldmfd sp!, {r1-r2}
mov pc, lr
export LED4_ON
LED4_ON
stmfd sp!, {r1-r2}
ldr r1, =GPFDAT
ldr r2, [r1]
orr r2, r2, #0x10
str r2, [r1]
ldmfd sp!, {r1-r2}
mov pc, lr
export LED5_ON
LED5_ON
stmfd sp!, {r1-r2}
ldr r1, =GPFDAT
ldr r2, [r1]
orr r2, r2, #0x20
str r2, [r1]
ldmfd sp!, {r1-r2}
mov pc, lr
export LED4_OFF
LED4_OFF
stmfd sp!, {r1-r2}
ldr r1, =GPFDAT
ldr r2, [r1]
bic r2, r2, #0x10
str r2, [r1]
ldmfd sp!, {r1-r2}
mov pc, lr
export LED5_OFF
LED5_OFF
stmfd sp!, {r1-r2}
ldr r1, =GPFDAT
ldr r2, [r1]
bic r2, r2, #0x20
str r2, [r1]
ldmfd sp!, {r1-r2}
mov pc, lr
;===============================================================
;Read a nand flash page(512 bytes), K9F1208U0C nand flash
;Input r0:save to, r1:NFDATA
;===============================================================
export NF_K9F1208U0C_ReadPage
macro
NF_K9F1208U0C_ReadWord $src, $det, $tmp
[ __BIG_ENDIAN
ldrb $tmp, [$src]
mov $det, $tmp, lsl #24
ldrb $tmp, [$src]
orr $det, $det, $tmp, lsl #16
ldrb $tmp, [$src]
orr $det, $det, $tmp, lsl #8
ldrb $tmp, [$src]
orr $det, $det, $tmp
|
ldrb $det, [$src]
ldrb $tmp, [$src]
orr $det, $det, $tmp, lsl #8
ldrb $tmp, [$src]
orr $det, $det, $tmp, lsl #16
ldrb $tmp, [$src]
orr $det, $det, $tmp, lsl #24
]
mend
NF_K9F1208U0C_ReadPage
stmfd sp!, {r2-r11}
mov r2, #0x200
0
NF_K9F1208U0C_ReadWord r1, r4, r3
NF_K9F1208U0C_ReadWord r1, r5, r3
NF_K9F1208U0C_ReadWord r1, r6, r3
NF_K9F1208U0C_ReadWord r1, r7, r3
NF_K9F1208U0C_ReadWord r1, r8, r3
NF_K9F1208U0C_ReadWord r1, r9, r3
NF_K9F1208U0C_ReadWord r1, r10, r3
NF_K9F1208U0C_ReadWord r1, r11, r3
stmia r0!, {r4-r11}
subs r2, r2, #32
bne %b0
ldmfd sp!, {r2-r11}
mov pc, lr
;========================================================================
;memory copy
;Input r0:from, r1:to, r2:size
;========================================================================
export WordCopy
WordCopy
stmfd sp!, {r0-r11}
cmp r0, r1
beq WordCopyEnd
bcc WordCopyToHighAddr
WordCopyToLowAddr
movs r3, r2, lsr #3
beq %f1
0
ldmia r0!, {r4-r11}
stmia r1!, {r4-r11}
subs r3, r3, #1
bne %b0
1
ands r2, r2, #7
beq WordCopyEnd
2
ldr r3, [r0], #4
str r3, [r1], #4
subs r2, r2, #1
bne %b2
b WordCopyEnd
WordCopyToHighAddr
add r0, r0, r2
add r1, r1, r2
movs r3, r2, lsr #3
beq %f1
0
ldmdb r0!, {r4-r11}
stmdb r1!, {r4-r11}
subs r3, r3, #1
bne %b0
1
ands r2, r2, #7
beq WordCopyEnd
2
ldr r3, [r0, #-4]!
str r3, [r1, #-4]!
subs r2, r2, #1
bne %b2
WordCopyEnd
ldmfd sp!, {r0-r11}
mov pc, lr
export ByteCopy
ByteCopy
stmfd sp!, {r3-r5, lr}
mov r3, r2
movs r2, r2, lsr #2
beq %f0
blne WordCopy
0
ands r2, r3, #3
beq %f1
mov r3, r3, lsr #2
mov r3, r3, lsl #2
add r0, r0, r3
add r1, r1, r3
ldrb r3, [r0, #1]
ldrb r4, [r0, #1]
ldrb r5, [r0, #1]
strb r3, [r1, #1]
subs r2, r2, #1
beq %f1
strb r4, [r1, #1]
subs r2, r2, #1
beq %f1
strb r5, [r1, #1]
1
ldmfd sp!, {r3-r5, pc}
;========================================================================
ltorg
SMRDATA data
dcd BWSCON_DATA
dcd BCON0_DATA
dcd BCON1_DATA
dcd BCON2_DATA
dcd BCON3_DATA
dcd BCON4_DATA
dcd BCON5_DATA
dcd BCON6_DATA
dcd BCON7_DATA
dcd REFRESH_DATA
dcd BANKSIZE_DATA
dcd MRSRB6_DATA
dcd MRSRB7_DATA
area InterruptHandle, data, readwrite
^ _ISR_STARTADDRESS
;store the handler's entry address
Addr_ResetHandle # 4 ;reset-handle must be preseted
Addr_UndefHandle # 4
Addr_SWIHandle # 4
Addr_HandlePabort # 4
Addr_HandleDabort # 4
Addr_HandleReserved # 4
Addr_HandleIRQ # 4
Addr_HandleFIQ # 4
;store the irq handler's address
ADDR_HandleEINT0 # 4
ADDR_HandleEINT1 # 4
ADDR_HandleEINT2 # 4
ADDR_HandleEINT3 # 4
ADDR_HandleEINT4_7 # 4
ADDR_HandleEINT8_23 # 4
ADDR_HandleRSV6 # 4 ;reserved
ADDR_HandleBATFLT # 4
ADDR_HandleTICK # 4
ADDR_HandleWDT # 4
ADDR_HandleTIMER0 # 4
ADDR_HandleTIMER1 # 4
ADDR_HandleTIMER2 # 4
ADDR_HandleTIMER3 # 4
ADDR_HandleTIMER4 # 4
ADDR_HandleUART2 # 4
ADDR_HandleLCD # 4
ADDR_HandleDMA0 # 4
ADDR_HandleDMA1 # 4
ADDR_HandleDMA2 # 4
ADDR_HandleDMA3 # 4
ADDR_HandleMMC # 4
ADDR_HandleSPI0 # 4
ADDR_HandleUART1 # 4
ADDR_HandleRSV24 # 4
ADDR_HandleUSBD # 4
ADDR_HandleUSBH # 4
ADDR_HandleIIC # 4
ADDR_HandleUART0 # 4
ADDR_HandleSPI1 # 4
ADDR_HandleRTC # 4
ADDR_HandleADC # 4
end
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