libs.s

一个简单的基于s3c2410的bootloader

;==================================================
;	libs.s
;====================================================
R1_I	EQU	(1<<12)
R1_C	EQU	(1<<2)
R1_A	EQU	(1<<1)
R1_M    EQU	(1)
R1_iA	EQU	(1<<31)
R1_nF   EQU	(1<<30)
	include addr.s
	area libscode, code, readonly
	
;these functions works only if the processor is in previliged mode.
;void Set_IF( void )
;set I, F bit to disable IRQ, FIQ
	export Set_IF
Set_IF
	mrs		r0, cpsr;
	orr		r0, r0, #NOINT
	msr		cpsr_cxsf, r0
	mov		pc, lr
;void Clear_IF( void )
;clear I, F bit to enable IRQ, FIQ
	export Clear_IF
Clear_IF
	mrs		r0, cpsr;
	bic		r0, r0, #NOINT
	msr		cpsr_cxsf, r0
	mov		pc, lr
	
;void MMU_SetAsyncBusMode( void ) 
; FCLK:HCLK= 1:2
	export MMU_SetAsyncBusMode
MMU_SetAsyncBusMode
	mrc	p15, 0, r0, c1, c0, 0
	orr	r0, r0, #R1_nF:OR:R1_iA
	mcr	p15, 0, r0, c1, c0, 0
	mov	pc, lr
   
;void MMU_SetFastBusMode( void )
; FCLK:HCLK= 1:1
	export MMU_SetFastBusMode
MMU_SetFastBusMode
	mrc	p15, 0, r0, c1, c0, 0
	bic r0, r0, #R1_nF:OR:R1_iA
	mcr	p15, 0, r0, c1, c0, 0
	mov	pc, lr
;void MMU_EnableICache( void )
   export MMU_EnableICache
MMU_EnableICache	
	mrc 	p15, 0, r0, c1, c0, 0
	orr 	r0, r0, #R1_I
	mcr 	p15, 0, r0, c1, c0, 0
	mov		pc, lr
    
   end