memoryconfig.s

一个简单的基于s3c2410的bootloader

;====================================================================
; Memory Controller Configuration
;	MemoryConfig.s
;====================================================================
;Bank Width, nWait signal enable, UB/LB setting
DW8				equ	(0x0)
DW16			equ	(0x1)
DW32			equ	(0x2)
WAIT			equ	(0x1<<2)
UBLB			equ	(0x1<<3)

B0_BWSCON		equ (0)		;read only
B1_BWSCON		equ (DW32)
B2_BWSCON		equ (DW16)
B3_BWSCON		equ (DW16)
B4_BWSCON		equ (DW16)
B5_BWSCON		equ (DW16)
B6_BWSCON		equ (DW32)
B7_BWSCON		equ (DW32)

BWSCON_DATA		equ (B0_BWSCON+(B1_BWSCON<<4)+(B2_BWSCON<<8)+\
				(B3_BWSCON<<12)+(B4_BWSCON<<16)+(B5_BWSCON<<20)+\
				(B6_BWSCON<<24)+(B7_BWSCON<<28))
;====================================================================
;Bank Controller Register
B0_Tacs			equ	0x0	;2bit,	00 = 0 clock 	01 = 1 clock
						;		10 = 2 clocks 	11 = 4 clocks 	
B0_Tcos			equ	0x0	;2bit,	00 = 0 clock 	01 = 1 clock
						;		10 = 2 clocks 	11 = 4 clocks 	
B0_Tacc			equ	0x7	;3bit,	000 = 1 clock 001 = 2 clocks
						;		010 = 3 clocks 011 = 4 clocks
						;		100 = 6 clocks 101 = 8 clocks
						;		110 = 10 clocks 111 = 14 clocks
B0_Tcoh			equ	0x0	;2bit,	00 = 0 clock 	01 = 1 clock
						;		10 = 2 clocks 	11 = 4 clocks 	
B0_Tah			equ	0x0	;2bit,	00 = 0 clock 	01 = 1 clock
						;		10 = 2 clocks 	11 = 4 clocks
B0_Tacp			equ	0x0	;2bit,	00 = 2 clocks 	01 = 3 clocks
						;		10 = 4 clocks 	11 = 6 clocks
B0_PMC			equ	0x0	;2bit,	00 = normal (1 data) 01 = 4 data
						;		10 = 8 data 11 = 16 data

B1_Tacs			equ	0x0	;0clk
B1_Tcos			equ	0x0	;0clk
B1_Tacc			equ	0x7	;14clk
B1_Tcoh			equ	0x0	;0clk
B1_Tah			equ	0x0	;0clk
B1_Tacp			equ	0x0	
B1_PMC			equ	0x0	;normal

B2_Tacs			equ	0x0	;0clk
B2_Tcos			equ	0x0	;0clk
B2_Tacc			equ	0x7	;14clk
B2_Tcoh			equ	0x0	;0clk
B2_Tah			equ	0x0	;0clk
B2_Tacp			equ	0x0	
B2_PMC			equ	0x0	;normal

B3_Tacs			equ	0x0	;0clk
B3_Tcos			equ	0x0	;0clk
B3_Tacc			equ	0x7	;14clk
B3_Tcoh			equ	0x0	;0clk
B3_Tah			equ	0x0	;0clk
B3_Tacp			equ	0x0	
B3_PMC			equ	0x0	;normal

B4_Tacs			equ	0x0	;0clk
B4_Tcos			equ	0x0	;0clk
B4_Tacc			equ	0x7	;14clk
B4_Tcoh			equ	0x0	;0clk
B4_Tah			equ	0x0	;0clk
B4_Tacp			equ	0x0	
B4_PMC			equ	0x0	;normal

B5_Tacs			equ	0x0	;0clk
B5_Tcos			equ	0x0	;0clk
B5_Tacc			equ	0x7	;14clk
B5_Tcoh			equ	0x0	;0clk
B5_Tah			equ	0x0	;0clk
B5_Tacp			equ	0x0	
B5_PMC			equ	0x0	;normal

B6_Tacs			equ	0x0	;0clk
B6_Tcos			equ	0x0	;0clk
B6_Tacc			equ	0x7	;14clk
B6_Tcoh			equ	0x0	;0clk
B6_Tah			equ	0x0	;0clk
B6_Tacp			equ	0x0	
B6_PMC			equ	0x0	;normal

B7_Tacs			equ	0x0	;0clk
B7_Tcos			equ	0x0	;0clk
B7_Tacc			equ	0x7	;14clk
B7_Tcoh			equ	0x0	;0clk
B7_Tah			equ	0x0	;0clk
B7_Tacp			equ	0x0	
B7_PMC			equ	0x0	;normal

B6_MT			equ	0x3	;SDRAM
;B6_Trcd			equ	0x0	;2clk
B6_Trcd			equ	0x1	;3clk
B6_SCAN			equ	0x1	;9bit

B7_MT			equ	0x3	;SDRAM
;B7_Trcd			equ	0x0	;2clk
B7_Trcd			equ	0x1	;3clk
B7_SCAN			equ	0x1	;9bit

BCON0_DATA		equ ((B0_Tacs<<13)+(B0_Tcos<<11)+(B0_Tacc<<8)+\
				(B0_Tcoh<<6)+(B0_Tah<<4)+(B0_Tacp<<2)+(B0_PMC))
BCON1_DATA		equ ((B1_Tacs<<13)+(B1_Tcos<<11)+(B1_Tacc<<8)+\
				(B1_Tcoh<<6)+(B1_Tah<<4)+(B1_Tacp<<2)+(B1_PMC))
BCON2_DATA		equ ((B2_Tacs<<13)+(B2_Tcos<<11)+(B2_Tacc<<8)+\
				(B2_Tcoh<<6)+(B2_Tah<<4)+(B2_Tacp<<2)+(B2_PMC))
BCON3_DATA		equ ((B3_Tacs<<13)+(B3_Tcos<<11)+(B3_Tacc<<8)+\
				(B3_Tcoh<<6)+(B3_Tah<<4)+(B3_Tacp<<2)+(B3_PMC))
BCON4_DATA		equ ((B4_Tacs<<13)+(B4_Tcos<<11)+(B4_Tacc<<8)+\
				(B4_Tcoh<<6)+(B4_Tah<<4)+(B4_Tacp<<2)+(B4_PMC))
BCON5_DATA		equ ((B5_Tacs<<13)+(B5_Tcos<<11)+(B5_Tacc<<8)+\
				(B5_Tcoh<<6)+(B5_Tah<<4)+(B5_Tacp<<2)+(B5_PMC))
BCON6_DATA		equ	((B6_MT<<15)+(B6_Trcd<<2)+(B6_SCAN))
BCON7_DATA		equ	((B7_MT<<15)+(B7_Trcd<<2)+(B7_SCAN))
;====================================================================
;SDRAM refresh control
REFEN			equ	0x1	;SDRAM Refresh enable, 0=Disable, 1=Enable(self/auto refresh)
TREFMD			equ	0x0	;SDRAM Refresh Mode, 0=Auto Refresh, 1=Self Refresh
Trp				equ	0x0	;SDRAM RAS pre-charge Time
					;		00 = 2 clocks 01 = 3 clocks 
					;		10 = 4 clocks 11 = Not support
Tsrc			equ	0x3	;SDRAM Semi Row Cycle Time
					;		00 = 4 clocks 01 = 5 clocks 
Tchr			equ	0x2	;3clk, S3C2410 not used pin
REFCNT			equ 1113;SDRAM refresh count value
					;		Refresh period = (2<<11-REFCNT+1)/HCLK

REFRESH_DATA equ ((REFEN<<23)+(TREFMD<<22)+(Trp<<20)+(Tsrc<<18)+(Tchr<<16)+REFCNT)
;====================================================================
;ARM core burst operation, SDRAM SCLK, SCKE enable control, 
BURST_EN		equ (1<<7)
SCKE_EN			equ (1<<5)
SCLK_EN			equ (1<<4)
BK76MAP			equ 0x2	;BANK6/7 memory map
					;	010 = 128MB/128MB 	001 = 64MB/64MB
					;	000 = 32M/32M 		111 = 16M/16M
					;	110 = 8M/8M 		101 = 4M/4M
					;	100 = 2M/2M

BANKSIZE_DATA equ (SCKE_EN+SCLK_EN+BK76MAP)		;SCLK power saving mode, BANKSIZE 128M/128M
;====================================================================
;SDRAM Mode register set for BANK6/7
B6_WBL			equ 0x0	;Write burst length
					;0: Burst (Fixed), 1: Reserved
B6_TM			equ 0x0	;Test mode
					;	00: Mode register set (Fixed)
					;	01, 10 and 11: Reserved
B6_CL			equ 0x3	;CAS latency
					;	000 = 1 clock, 010 = 2 clocks, 011=3 clocks
					;	Others: reserved
B6_BT			equ 0x0	;Burst type
					;	0: Sequential (Fixed), 1: Reserved
B6_BL			equ 0x0	;Burst length
					;	000: 1 (Fixed), Others: Reserved

B7_WBL			equ 0x0
B7_TM			equ 0x0
B7_CL			equ 0x3
B7_BT			equ 0x0
B7_BL			equ 0x0

MRSRB6_DATA 	equ ((B6_WBL<<9)+(B6_TM<<7)+(B6_CL<<4)+(B6_BT<<3)+B6_BL)
MRSRB7_DATA 	equ ((B7_WBL<<9)+(B7_TM<<7)+(B7_CL<<4)+(B7_BT<<3)+B6_BL)
;====================================================================
	end