addr.h

一个简单的基于s3c2410的bootloader

#define	rURXH2				( *( volatile U8 * )0x50008024)	//UART 2 Receive buffer
#endif
#define	WrUTXH0(ch)		rUTXH0 = (U8)(ch)
#define	RdURXH0()		rURXH0
#define	WrUTXH1(ch)		rUTXH1 = (U8)(ch)
#define	RdURXH1()		rURXH1
#define	WrUTXH2(ch)		rUTXH2 = (U8)(ch)
#define	RdURXH2()		rURXH2

// Usb	device
#ifdef __BIG_ENDIAN
<ERROR IF BIG_ENDIAN>
#define rFUNC_ADDR_REG		( *( volatile U8 * )0x52000143)	//Usb device address
#define rPWR_REG			( *( volatile U8 * )0x52000147)	//Power management
#define rEP_INT_REG			( *( volatile U8 * )0x5200014b)	//EP Interrupt pending and clear
#define rUSB_INT_REG		( *( volatile U8 * )0x5200015b)	//USB Interrupt pending and clear
#define rEP_INT_EN_REG		( *( volatile U8 * )0x5200015f)	//Interrupt enable
#define rUSB_INT_EN_REG		( *( volatile U8 * )0x5200016f)
#define rFRAME_NUM1_REG		( *( volatile U8 * )0x52000173)	//Frame number lower byte
#define rFRAME_NUM2_REG		( *( volatile U8 * )0x52000177)	//Frame number higher byte
#define rINDEX_REG			( *( volatile U8 * )0x5200017b)	//Register index
#define rMAXP_REG			( *( volatile U8 * )0x52000183)	//Endpoint max packet
#define rEP0_CSR			( *( volatile U8 * )0x52000187)	//Endpoint 0 status
#define rIN_CSR1_REG		( *( volatile U8 * )0x52000187)	//In endpoint control status
#define rIN_CSR2_REG		( *( volatile U8 * )0x5200018b)
#define rOUT_CSR1_REG		( *( volatile U8 * )0x52000193)	//Out endpoint control status
#define rOUT_CSR2_REG		( *( volatile U8 * )0x52000197)
#define rOUT_FIFO_CNT1_REG	( *( volatile U8 * )0x5200019b)	//Endpoint out write count
#define rOUT_FIFO_CNT2_REG	( *( volatile U8 * )0x5200019f)
#define rEP0_FIFO			( *( volatile U8 * )0x520001c3)	//Endpoint 0 FIFO
#define rEP1_FIFO			( *( volatile U8 * )0x520001c7)	//Endpoint 1 FIFO
#define rEP2_FIFO			( *( volatile U8 * )0x520001cb)	//Endpoint 2 FIFO
#define rEP3_FIFO			( *( volatile U8 * )0x520001cf)	//Endpoint 3 FIFO
#define rEP4_FIFO			( *( volatile U8 * )0x520001d3)	//Endpoint 4 FIFO
#define rEP1_DMA_CON		( *( volatile U8 * )0x52000203)	//EP1 DMA interface control
#define rEP1_DMA_UNIT		( *( volatile U8 * )0x52000207)	//EP1 DMA Tx unit counter
#define rEP1_DMA_FIFO		( *( volatile U8 * )0x5200020b)	//EP1 DMA Tx FIFO counter
#define rEP1_DMA_TTC_L		( *( volatile U8 * )0x5200020f)	//EP1 DMA total Tx counter
#define rEP1_DMA_TTC_M		( *( volatile U8 * )0x52000213)
#define rEP1_DMA_TTC_H		( *( volatile U8 * )0x52000217)
#define rEP2_DMA_CON		( *( volatile U8 * )0x5200021b)	//EP2 DMA interface control
#define rEP2_DMA_UNIT		( *( volatile U8 * )0x5200021f)	//EP2 DMA Tx unit counter
#define rEP2_DMA_FIFO		( *( volatile U8 * )0x52000223)	//EP2 DMA Tx FIFO counter
#define rEP2_DMA_TTC_L		( *( volatile U8 * )0x52000227)	//EP2 DMA total Tx counter
#define rEP2_DMA_TTC_M		( *( volatile U8 * )0x5200022b)
#define rEP2_DMA_TTC_H		( *( volatile U8 * )0x5200022f)
#define rEP3_DMA_CON		( *( volatile U8 * )0x52000243)	//EP3 DMA interface control
#define rEP3_DMA_UNIT		( *( volatile U8 * )0x52000247)	//EP3 DMA Tx unit counter
#define rEP3_DMA_FIFO		( *( volatile U8 * )0x5200024b)	//EP3 DMA Tx FIFO counter
#define rEP3_DMA_TTC_L		( *( volatile U8 * )0x5200024f)	//EP3 DMA total Tx counter
#define rEP3_DMA_TTC_M		( *( volatile U8 * )0x52000253)
#define rEP3_DMA_TTC_H		( *( volatile U8 * )0x52000257)
#define rEP4_DMA_CON		( *( volatile U8 * )0x5200025b)	//EP4 DMA interface control
#define rEP4_DMA_UNIT		( *( volatile U8 * )0x5200025f)	//EP4 DMA Tx unit counter
#define rEP4_DMA_FIFO		( *( volatile U8 * )0x52000263)	//EP4 DMA Tx FIFO counter
#define rEP4_DMA_TTC_L		( *( volatile U8 * )0x52000267)	//EP4 DMA total Tx counter
#define rEP4_DMA_TTC_M		( *( volatile U8 * )0x5200026b)
#define rEP4_DMA_TTC_H		( *( volatile U8 * )0x5200026f)

#else 	// Little Endian
#define rFUNC_ADDR_REG		( *( volatile U8 * )0x52000140)	//Function address
#define rPWR_REG			( *( volatile U8 * )0x52000144)	//Power management
#define rEP_INT_REG			( *( volatile U8 * )0x52000148)	//EP Interrupt pending and clear
#define rUSB_INT_REG		( *( volatile U8 * )0x52000158)	//USB Interrupt pending and clear
#define rEP_INT_EN_REG		( *( volatile U8 * )0x5200015c)	//Interrupt enable
#define rUSB_INT_EN_REG		( *( volatile U8 * )0x5200016c)
#define rFRAME_NUM1_REG		( *( volatile U8 * )0x52000170)	//Frame number lower byte
#define rFRAME_NUM2_REG		( *( volatile U8 * )0x52000174)	//Frame number higher byte
#define rINDEX_REG			( *( volatile U8 * )0x52000178)	//Register index
#define rMAXP_REG			( *( volatile U8 * )0x52000180)	//Endpoint max packet
#define rEP0_CSR			( *( volatile U8 * )0x52000184)	//Endpoint 0 status
#define rIN_CSR1_REG		( *( volatile U8 * )0x52000184)	//In endpoint control status
#define rIN_CSR2_REG		( *( volatile U8 * )0x52000188)
#define rOUT_CSR1_REG		( *( volatile U8 * )0x52000190)	//Out endpoint control status
#define rOUT_CSR2_REG		( *( volatile U8 * )0x52000194)
#define rOUT_FIFO_CNT1_REG	( *( volatile U8 * )0x52000198)	//Endpoint out write count
#define rOUT_FIFO_CNT2_REG	( *( volatile U8 * )0x5200019c)
#define rEP0_FIFO			( *( volatile U8 * )0x520001c0)	//Endpoint 0 FIFO
#define rEP1_FIFO			( *( volatile U8 * )0x520001c4)	//Endpoint 1 FIFO
#define rEP2_FIFO			( *( volatile U8 * )0x520001c8)	//Endpoint 2 FIFO
#define rEP3_FIFO			( *( volatile U8 * )0x520001cc)	//Endpoint 3 FIFO
#define rEP4_FIFO			( *( volatile U8 * )0x520001d0)	//Endpoint 4 FIFO
#define rEP1_DMA_CON		( *( volatile U8 * )0x52000200)	//EP1 DMA interface control
#define rEP1_DMA_UNIT		( *( volatile U8 * )0x52000204)	//EP1 DMA Tx unit counter
#define rEP1_DMA_FIFO		( *( volatile U8 * )0x52000208)	//EP1 DMA Tx FIFO counter
#define rEP1_DMA_TTC_L		( *( volatile U8 * )0x5200020c)	//EP1 DMA total Tx counter
#define rEP1_DMA_TTC_M		( *( volatile U8 * )0x52000210)
#define rEP1_DMA_TTC_H		( *( volatile U8 * )0x52000214)
#define rEP2_DMA_CON		( *( volatile U8 * )0x52000218)	//EP2 DMA interface control
#define rEP2_DMA_UNIT		( *( volatile U8 * )0x5200021c)	//EP2 DMA Tx unit counter
#define rEP2_DMA_FIFO		( *( volatile U8 * )0x52000220)	//EP2 DMA Tx FIFO counter
#define rEP2_DMA_TTC_L		( *( volatile U8 * )0x52000224)	//EP2 DMA total Tx counter
#define rEP2_DMA_TTC_M		( *( volatile U8 * )0x52000228)
#define rEP2_DMA_TTC_H		( *( volatile U8 * )0x5200022c)
#define rEP3_DMA_CON		( *( volatile U8 * )0x52000240)	//EP3 DMA interface control
#define rEP3_DMA_UNIT		( *( volatile U8 * )0x52000244)	//EP3 DMA Tx unit counter
#define rEP3_DMA_FIFO		( *( volatile U8 * )0x52000248)	//EP3 DMA Tx FIFO counter
#define rEP3_DMA_TTC_L		( *( volatile U8 * )0x5200024c)	//EP3 DMA total Tx counter
#define rEP3_DMA_TTC_M		( *( volatile U8 * )0x52000250)
#define rEP3_DMA_TTC_H		( *( volatile U8 * )0x52000254)
#define rEP4_DMA_CON		( *( volatile U8 * )0x52000258)	//EP4 DMA interface control
#define rEP4_DMA_UNIT		( *( volatile U8 * )0x5200025c)	//EP4 DMA Tx unit counter
#define rEP4_DMA_FIFO		( *( volatile U8 * )0x52000260)	//EP4 DMA Tx FIFO counter
#define rEP4_DMA_TTC_L		( *( volatile U8 * )0x52000264)	//EP4 DMA total Tx counter
#define rEP4_DMA_TTC_M		( *( volatile U8 * )0x52000268)
#define rEP4_DMA_TTC_H		( *( volatile U8 * )0x5200026c)
#endif


//	Watch dog timer
#define	rWTCON				( *( volatile U32 * )0x53000000)	//Watchdog timer control
#define rWTDAT				( *( volatile U32 * )0x53000004)	//
#define rWTCNT				( *( volatile U32 * )0x53000008)	//


//	I/O Ports
#define	rGPACON				( *( volatile U32 * )0x56000000)	//Port A control
#define	rGPADAT				( *( volatile U32 * )0x56000004)	//Port A data
#define	rGPBCON				( *( volatile U32 * )0x56000010)	//Port B control
#define	rGPBDAT				( *( volatile U32 * )0x56000014)	//Port B data
#define	rGPBUP				( *( volatile U32 * )0x56000018)	//Port B pull-up control
#define	rGPCCON				( *( volatile U32 * )0x56000020)	//Port C control
#define	rGPCDAT				( *( volatile U32 * )0x56000024)	//Port C data
#define	rGPCUP				( *( volatile U32 * )0x56000028)	//Port C pull-up control
#define	rGPDCON				( *( volatile U32 * )0x56000030)	//Port D control
#define	rGPDDAT				( *( volatile U32 * )0x56000034)	//Port D data
#define	rGPDUP				( *( volatile U32 * )0x56000038)	//Port D pull-up control
#define	rGPECON				( *( volatile U32 * )0x56000040)	//Port E control
#define	rGPEDAT				( *( volatile U32 * )0x56000044)	//Port E data
#define	rGPEUP				( *( volatile U32 * )0x56000048)	//Port E pull-up control
#define	rGPFCON				( *( volatile U32 * )0x56000050)	//Port F control
#define	rGPFDAT				( *( volatile U32 * )0x56000054)	//Port F data
#define	rGPFUP				( *( volatile U32 * )0x56000058)	//Port F pull-up control
#define	rGPGCON				( *( volatile U32 * )0x56000060)	//Port G control
#define	rGPGDAT				( *( volatile U32 * )0x56000064)	//Port G data
#define	rGPGUP				( *( volatile U32 * )0x56000068)	//Port G pull-up control
#define	rGPHCON				( *( volatile U32 * )0x56000070)	//Port H control
#define	rGPHDAT				( *( volatile U32 * )0x56000074)	//Port H data
#define	rGPHUP				( *( volatile U32 * )0x56000078)	//Port H pull-up control
#define	rMISCCR				( *( volatile U32 * )0x56000080)	//Miscellaneous control
#define	rDCLKCON			( *( volatile U32 * )0x56000084)	//DCLK0/1 control
#define	rEXTINT0			( *( volatile U32 * )0x56000088)	//External interrupts signaling methods register 0
#define	rEXTINT1			( *( volatile U32 * )0x5600008C)	//External interrupts signaling methods register 1
#define	rEXTINT2			( *( volatile U32 * )0x56000090)	//External interrupts signaling methods register 2
#define	rEINTFLT0			( *( volatile U32 * )0x56000094)	//Reserved
#define	rEINTFLT1			( *( volatile U32 * )0x56000098)	//Reserved
#define	rEINTFLT2			( *( volatile U32 * )0x5600009C)	//External interrupt filter control register 2
#define	rEINTFLT3			( *( volatile U32 * )0x560000A0)	//External interrupt filter control register 3
#define	rEINTMASK			( *( volatile U32 * )0x560000A4)	//External interrupt mask
#define	rEINTPEND			( *( volatile U32 * )0x560000A8)	//External interrupt pending
#define	rGSTATUS0			( *( volatile U32 * )0x560000AC)	//External pin status
#define	rGSTATUS1			( *( volatile U32 * )0x560000B0)	//Chip ID	(0x32410002)
#define	rGSTATUS2			( *( volatile U32 * )0x560000B4)	//Reset type
#define	rGSTATUS3			( *( volatile U32 * )0x560000B8)	//Saved data0(32-bit) before entering POWER_OFF mode
#define	rGSTATUS4			( *( volatile U32 * )0x560000BC)	//Saved data0(32-bit) before entering POWER_OFF mode

#endif