addr.h

一个简单的基于s3c2410的bootloader

//===================================================================
//	Addr.h
//===================================================================
#ifndef __ADDR_H__
#define	__ADDR_H__

#include "def.h"

//	Interrupt register
#define	rSRCPND				( *( volatile U32 * )0x4A000000)	//Interrupt source pending status
#define	rINTMOD				( *( volatile U32 * )0X4A000004)	//Interrupt mode control
#define	rINTMSK 			( *( volatile U32 * )0x4A000008)	//Interrupt mask control
#define	rPRIORITY			( *( volatile U32 * )0x4A00000C)	//Interrupt request priority control
#define	rINTPND				( *( volatile U32 * )0x4A000010)	//Interrupt request status
#define	rINTOFFSET			( *( volatile U32 * )0x4A000014)	//Interruot request source offset
#define	rSUBSRCPND			( *( volatile U32 * )0x4A000018)	//Interrupt sub source pending status
#define	rINTSUBMSK			( *( volatile U32 * )0X4A00001C)	//Interrupt sub mask control
#define	BIT_EINT0			(0x1)			//	Interrupt Pending bits define
#define	BIT_EINT1			(0x1<<1)		//
#define	BIT_EINT2			(0x1<<2)		//
#define	BIT_EINT3			(0x1<<3)		//
#define	BIT_EINT4_7			(0x1<<4)		//
#define	BIT_EINT8_23		(0x1<<5)		//
#define	BIT_NOTUSED6		(0x1<<6)		//
#define	BIT_BAT_FLT			(0x1<<7)		//
#define	BIT_TICK			(0x1<<8)		//
#define	BIT_WDT				(0x1<<9)		//
#define	BIT_TIMER0			(0x1<<10)		//
#define	BIT_TIMER1			(0x1<<11)		//
#define	BIT_TIMER2			(0x1<<12)		//
#define	BIT_TIMER3			(0x1<<13)		//
#define	BIT_TIMER4			(0x1<<14)		//
#define	BIT_UART2			(0x1<<15)		//
#define	BIT_LCD				(0x1<<16)		//
#define	BIT_DMA0			(0x1<<17)		//
#define	BIT_DMA1			(0x1<<18)		//
#define	BIT_DMA2			(0x1<<19)		//
#define	BIT_DMA3			(0x1<<20)		//
#define	BIT_SDI				(0x1<<21)		//
#define	BIT_SPI0			(0x1<<22)		//
#define	BIT_UART1			(0x1<<23)		//
#define	BIT_NOTUSED24		(0x1<<24)		//
#define	BIT_USBD			(0x1<<25)		//
#define	BIT_USBH			(0x1<<26)		//
#define	BIT_IIC				(0x1<<27)		//
#define	BIT_UART0			(0x1<<28)		//
#define	BIT_SPI1			(0x1<<29)		//
#define	BIT_RTC				(0x1<<30)		//
#define	BIT_ADC				(0x1<<31)		//
#define	BIT_ALLMSK			(0xFFFFFFFF)	//
#define	BIT_SUB_ALLMSK		(0x7FF)			//
#define	BIT_SUB_ADC			(0x1<<10)		//
#define	BIT_SUB_TC			(0x1<<9)		//
#define	BIT_SUB_ERR2		(0x1<<8)		//
#define	BIT_SUB_TXD2		(0x1<<7)		//
#define	BIT_SUB_RXD2		(0x1<<6)		//
#define	BIT_SUB_ERR1		(0x1<<5)		//
#define	BIT_SUB_TXD1		(0x1<<4)		//
#define	BIT_SUB_RXD1		(0x1<<3)		//
#define	BIT_SUB_ERR0		(0x1<<2)		//
#define	BIT_SUB_TXD0		(0x1<<1)		//
#define	BIT_SUB_RXD0		(0x1<<0)		//

//	DMA Control
#define	rDISRC0				( *( volatile U32 * )0x4B000000)	//DMA 0 initial source start address
#define	rDISRCC0			( *( volatile U32 * )0x4B000004)	//DMA 0 initial source control
#define	rDIDST0				( *( volatile U32 * )0x4B000008)	//DMA 0 initial destination start address
#define	rDIDSTC0			( *( volatile U32 * )0x4B00000C)	//DMA 0 initial destination control
#define	rDCON0				( *( volatile U32 * )0x4B000010)	//DMA 0 control register
#define	rDSTAT0				( *( volatile U32 * )0x4B000014)	//DMA 0 count register
#define	rDCSRC0				( *( volatile U32 * )0x4B000018)	//DMA 0 Current source address
#define	rDCDST0				( *( volatile U32 * )0x4B00001C)	//DMA 0 current destination address
#define	rDMASKTRIG0			( *( volatile U32 * )0x4B000020)	//DMA 0 mask trigger register
#define	rDISRC1				( *( volatile U32 * )0x4B000040)	//DMA 1 initial source start address
#define	rDISRCC1			( *( volatile U32 * )0x4B000044)	//DMA 1 initial source control
#define	rDIDST1				( *( volatile U32 * )0x4B000048)	//DMA 1 initial destination start address
#define	rDIDSTC1			( *( volatile U32 * )0x4B00004C)	//DMA 1 initial destination control
#define	rDCON1				( *( volatile U32 * )0x4B000050)	//DMA 1 control register
#define	rDSTAT1				( *( volatile U32 * )0x4B000054)	//DMA 1 count register
#define	rDCSRC1				( *( volatile U32 * )0x4B000058)	//DMA 1 Current source address
#define	rDCDST1				( *( volatile U32 * )0x4B00005C)	//DMA 1 current destination address
#define	rDMASKTRIG1			( *( volatile U32 * )0x4B000060)	//DMA 1 mask trigger register
#define	rDISRC2				( *( volatile U32 * )0x4B000080)	//DMA 2 initial source start address
#define	rDISRCC2			( *( volatile U32 * )0x4B000084)	//DMA 2 initial source control
#define	rDIDST2				( *( volatile U32 * )0x4B000088)	//DMA 2 initial destination start address
#define	rDIDSTC2			( *( volatile U32 * )0x4B00008C)	//DMA 2 initial destination control
#define	rDCON2				( *( volatile U32 * )0x4B000090)	//DMA 2 control register
#define	rDSTAT2				( *( volatile U32 * )0x4B000094)	//DMA 2 count register
#define	rDCSRC2				( *( volatile U32 * )0x4B000098)	//DMA 2 Current source address
#define	rDCDST2				( *( volatile U32 * )0x4B00009C)	//DMA 2 current destination address
#define	rDMASKTRIG2			( *( volatile U32 * )0x4B0000A0)	//DMA 2 mask trigger register
#define	rDISRC3				( *( volatile U32 * )0x4B0000C0)	//DMA 3 initial source start address
#define	rDISRCC3			( *( volatile U32 * )0x4B0000C4)	//DMA 3 initial source control
#define	rDIDST3				( *( volatile U32 * )0x4B0000C8)	//DMA 3 initial destination start address
#define	rDIDSTC3			( *( volatile U32 * )0x4B0000CC)	//DMA 3 initial destination control
#define	rDCON3				( *( volatile U32 * )0x4B0000D0)	//DMA 3 control register
#define	rDSTAT3				( *( volatile U32 * )0x4B0000D4)	//DMA 3 count register
#define	rDCSRC3				( *( volatile U32 * )0x4B0000D8)	//DMA 3 Current source address
#define	rDCDST3				( *( volatile U32 * )0x4B0000DC)	//DMA 3 current destination address
#define	rDMASKTRIG3			( *( volatile U32 * )0x4B0000E0)	//DMA 3 mask trigger register

//	Clock control
#define	rLOCKTIME			( *( volatile U32 * )0x4C000000)	//PLL lock time counter
#define	rMPLLCON			( *( volatile U32 * )0x4C000004)	//MPLL control
#define	rUPLLCON			( *( volatile U32 * )0x4C000008)	//UPLL control
#define	rCLKCON				( *( volatile U32 * )0x4C00000C)	//Clock generator control
#define	rCLKSLOW			( *( volatile U32 * )0x4c000010)	//Slow clock control
#define	rCLKDIVN			( *( volatile U32 * )0x4C000014)	//Clock divider control

//	K9S1208 nand flash
#define	rNFCONF				( *( volatile U32 * )0x4e000000)	//NAND flash control register
#define	rNFCMD				( *( volatile U32 * )0x4e000004)	//NAND flash memory command value
#define	rNFADDR				( *( volatile U8 * )0x4e000008)	//NAND flash memory address value
#define	rNFDATA				( *( volatile U8 * )0x4e00000C)	//NAND flash read/program data value
#define	rNFSTAT				( *( volatile U8 * )0x4e000010)	//NAND flash operation status
#define	rNFECC				( *( volatile U32 * )0x4e000014)	//NAND flash data register

//	Uart register
#define	rULCON0				( *( volatile U32 * )0x50000000)	//UART 0 Line control
#define	rUCON0				( *( volatile U32 * )0x50000004)	//UART 0 Control
#define	rUFCON0				( *( volatile U32 * )0x50000008)	//UART 0 FIFO control
#define	rUMCON0				( *( volatile U32 * )0x5000000C)	//UART 0 Modem control
#define	rUTRSTAT0			( *( volatile U32 * )0x50000010)	//UART 0 Tx/Rx status
#define	rUERSTAT0			( *( volatile U32 * )0x50000014)	//UART 0 RX error status
#define	rUFSTAT0			( *( volatile U32 * )0x50000018)	//UART 0 FIFO status
#define	rUMSTAT0			( *( volatile U32 * )0x5000001C)	//UART 0 Modem status
#define	rUBRDIV0			( *( volatile U32 * )0x50000028)	//UART 0 Baud rate divisor
#define	rULCON1				( *( volatile U32 * )0x50004000)	//UART 0 Line control
#define	rUCON1				( *( volatile U32 * )0x50004004)	//UART 0 Control
#define	rUFCON1				( *( volatile U32 * )0x50004008)	//UART 0 FIFO control
#define	rUMCON1				( *( volatile U32 * )0x5000400C)	//UART 0 Modem control
#define	rUTRSTAT1			( *( volatile U32 * )0x50004010)	//UART 0 Tx/Rx status
#define	rUERSTAT1			( *( volatile U32 * )0x50004014)	//UART 0 RX error status
#define	rUFSTAT1			( *( volatile U32 * )0x50004018)	//UART 0 FIFO status
#define	rUMSTAT1			( *( volatile U32 * )0x5000401C)	//UART 0 Modem status
#define	rUBRDIV1			( *( volatile U32 * )0x50004028)	//UART 0 Baud rate divisor
#define	rULCON2				( *( volatile U32 * )0x50008000)	//UART 0 Line control
#define	rUCON2				( *( volatile U32 * )0x50008004)	//UART 0 Control
#define	rUFCON2				( *( volatile U32 * )0x50008008)	//UART 0 FIFO control
#define	rUMCON2				( *( volatile U32 * )0x5000800C)	//UART 0 Modem control
#define	rUTRSTAT2			( *( volatile U32 * )0x50008010)	//UART 0 Tx/Rx status
#define	rUERSTAT2			( *( volatile U32 * )0x50008014)	//UART 0 RX error status
#define	rUFSTAT2			( *( volatile U32 * )0x50008018)	//UART 0 FIFO status
#define	rUBRDIV2			( *( volatile U32 * )0x50008028)	//UART 0 Baud rate divisor
#ifdef __BIG_ENDIAN		//	Big endian
#define	rUTXH0				( *( volatile U8 * )0x50000023)	//UART 0 Transmission Hold
#define	rURXH0				( *( volatile U8 * )0x50000027)	//UART 0 Receive buffer
#define	rUTXH1				( *( volatile U8 * )0x50004023)	//UART 1 Transmission Hold
#define	rURXH1				( *( volatile U8 * )0x50004027)	//UART 1 Receive buffer
#define	rUTXH2				( *( volatile U8 * )0x50008023)	//UART 2 Transmission Hold
#define	rURXH2				( *( volatile U8 * )0x50008027)	//UART 2 Receive buffer
#else					//	Little endian
#define	rUTXH0				( *( volatile U8 * )0x50000020)	//UART 0 Transmission Hold
#define	rURXH0				( *( volatile U8 * )0x50000024)	//UART 0 Receive buffer
#define	rUTXH1				( *( volatile U8 * )0x50004020)	//UART 1 Transmission Hold
#define	rURXH1				( *( volatile U8 * )0x50004024)	//UART 1 Receive buffer
#define	rUTXH2				( *( volatile U8 * )0x50008020)	//UART 2 Transmission Hold