📄 mainctrl.rpt
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-- Node name is 'cs'
-- Equation name is 'cs', type is output
cs = cnt2;
-- Node name is ':58' = 'devider0'
-- Equation name is 'devider0', location is LC3_B23, type is buried.
devider0 = DFFE( _EQ020, clk, VCC, VCC, VCC);
_EQ020 = !devider0 & !_LC2_B23;
-- Node name is ':57' = 'devider1'
-- Equation name is 'devider1', location is LC3_B16, type is buried.
devider1 = DFFE( _EQ021, clk, VCC, VCC, VCC);
_EQ021 = devider0 & !devider1 & !_LC2_B23
# !devider0 & devider1 & !_LC2_B23;
-- Node name is ':56' = 'devider2'
-- Equation name is 'devider2', location is LC5_B16, type is buried.
devider2 = DFFE( _EQ022, clk, VCC, VCC, VCC);
_EQ022 = !devider0 & devider2 & !_LC2_B23
# !devider1 & devider2 & !_LC2_B23
# devider0 & devider1 & !devider2 & !_LC2_B23;
-- Node name is ':55' = 'devider3'
-- Equation name is 'devider3', location is LC7_B16, type is buried.
devider3 = DFFE( _EQ023, clk, VCC, VCC, VCC);
_EQ023 = _LC2_B16 & !_LC2_B23;
-- Node name is ':54' = 'devider4'
-- Equation name is 'devider4', location is LC5_B23, type is buried.
devider4 = DFFE( _EQ024, clk, VCC, VCC, VCC);
_EQ024 = devider4 & !Div4 & !_LC4_B16
# !devider4 & !Div4 & _LC4_B16
# devider4 & !_LC4_B16 & _LC4_B23
# !devider4 & _LC4_B16 & _LC4_B23;
-- Node name is 'fc'
-- Equation name is 'fc', type is output
fc = _LC6_B23;
-- Node name is 'phase0'
-- Equation name is 'phase0', type is output
phase0 = counter8;
-- Node name is 'phase1'
-- Equation name is 'phase1', type is output
phase1 = counter9;
-- Node name is 'phase2'
-- Equation name is 'phase2', type is output
phase2 = counter10;
-- Node name is 'phase3'
-- Equation name is 'phase3', type is output
phase3 = counter11;
-- Node name is 'phase4'
-- Equation name is 'phase4', type is output
phase4 = counter12;
-- Node name is 'phase5'
-- Equation name is 'phase5', type is output
phase5 = counter13;
-- Node name is 'phase6'
-- Equation name is 'phase6', type is output
phase6 = counter14;
-- Node name is 'phase7'
-- Equation name is 'phase7', type is output
phase7 = counter15;
-- Node name is '|lpm_add_sub:117|addcore:adder|:67' from file "addcore.tdf" line 312, column 64
-- Equation name is '_LC4_B16', type is buried
_LC4_B16 = LCELL( _EQ025);
_EQ025 = devider0 & devider1 & devider2 & devider3;
-- Node name is '|lpm_add_sub:117|addcore:adder|:77' from file "addcore.tdf" line 316, column 45
-- Equation name is '_LC2_B16', type is buried
_LC2_B16 = LCELL( _EQ026);
_EQ026 = !devider2 & devider3
# !devider0 & devider3
# !devider1 & devider3
# devider0 & devider1 & devider2 & !devider3;
-- Node name is '|lpm_add_sub:118|addcore:adder|pcarry1' from file "addcore.tdf" line 312, column 40
-- Equation name is '_LC5_C19', type is buried
_LC5_C19 = LCELL( _EQ027);
_EQ027 = counter1 & PhaseM1
# counter0 & counter1 & PhaseM0
# counter0 & PhaseM0 & PhaseM1;
-- Node name is '|lpm_add_sub:118|addcore:adder|pcarry2' from file "addcore.tdf" line 312, column 40
-- Equation name is '_LC7_C19', type is buried
_LC7_C19 = LCELL( _EQ028);
_EQ028 = counter2 & _LC5_C19
# _LC5_C19 & PhaseM2
# counter2 & PhaseM2;
-- Node name is '|lpm_add_sub:118|addcore:adder|pcarry3' from file "addcore.tdf" line 312, column 40
-- Equation name is '_LC1_C19', type is buried
_LC1_C19 = LCELL( _EQ029);
_EQ029 = counter3 & _LC7_C19
# _LC7_C19 & PhaseM3
# counter3 & PhaseM3;
-- Node name is '|lpm_add_sub:118|addcore:adder|pcarry4' from file "addcore.tdf" line 312, column 40
-- Equation name is '_LC3_C20', type is buried
_LC3_C20 = LCELL( _EQ030);
_EQ030 = counter4 & _LC1_C19
# _LC1_C19 & PhaseM4
# counter4 & PhaseM4;
-- Node name is '|lpm_add_sub:118|addcore:adder|pcarry5' from file "addcore.tdf" line 312, column 40
-- Equation name is '_LC6_C20', type is buried
_LC6_C20 = LCELL( _EQ031);
_EQ031 = counter5 & _LC3_C20
# _LC3_C20 & PhaseM5
# counter5 & PhaseM5;
-- Node name is '|lpm_add_sub:118|addcore:adder|pcarry6' from file "addcore.tdf" line 312, column 40
-- Equation name is '_LC8_C20', type is buried
_LC8_C20 = LCELL( _EQ032);
_EQ032 = counter6 & _LC6_C20
# _LC6_C20 & PhaseM6
# counter6 & PhaseM6;
-- Node name is '|lpm_add_sub:118|addcore:adder|pcarry7' from file "addcore.tdf" line 312, column 40
-- Equation name is '_LC7_C18', type is buried
_LC7_C18 = LCELL( _EQ033);
_EQ033 = counter7 & _LC8_C20
# _LC8_C20 & PhaseM7
# counter7 & PhaseM7;
-- Node name is '|lpm_add_sub:118|addcore:adder|pcarry8' from file "addcore.tdf" line 312, column 40
-- Equation name is '_LC5_C18', type is buried
_LC5_C18 = LCELL( _EQ034);
_EQ034 = counter8 & _LC7_C18
# _LC7_C18 & PhaseM8
# counter8 & PhaseM8;
-- Node name is '|lpm_add_sub:118|addcore:adder|pcarry9' from file "addcore.tdf" line 312, column 40
-- Equation name is '_LC1_C22', type is buried
_LC1_C22 = LCELL( _EQ035);
_EQ035 = counter9 & _LC5_C18
# _LC5_C18 & PhaseM9
# counter9 & PhaseM9;
-- Node name is '|lpm_add_sub:118|addcore:adder|pcarry10' from file "addcore.tdf" line 312, column 40
-- Equation name is '_LC2_C20', type is buried
_LC2_C20 = LCELL( _EQ036);
_EQ036 = counter10 & _LC1_C22
# _LC1_C22 & PhaseM10
# counter10 & PhaseM10;
-- Node name is '|lpm_add_sub:118|addcore:adder|:147' from file "addcore.tdf" line 312, column 64
-- Equation name is '_LC1_C18', type is buried
_LC1_C18 = LCELL( _EQ037);
_EQ037 = counter11 & counter12 & _LC2_C20;
-- Node name is '~30~1'
-- Equation name is '~30~1', location is LC1_B23, type is buried.
-- synthesized logic cell
!_LC1_B23 = _LC1_B23~NOT;
_LC1_B23~NOT = LCELL( _EQ038);
_EQ038 = !devider0 & devider1 & Div0 & Div1
# !devider0 & !devider1 & Div0 & !Div1
# devider0 & !devider1 & !Div0 & Div1
# devider0 & devider1 & !Div0 & !Div1;
-- Node name is '~30~2'
-- Equation name is '~30~2', location is LC4_B23, type is buried.
-- synthesized logic cell
!_LC4_B23 = _LC4_B23~NOT;
_LC4_B23~NOT = LCELL( _EQ039);
_EQ039 = Div3 & _LC1_B16 & !_LC1_B23 & _LC2_B16
# !Div3 & _LC1_B16 & !_LC1_B23 & !_LC2_B16;
-- Node name is ':30'
-- Equation name is '_LC2_B23', type is buried
_LC2_B23 = LCELL( _EQ040);
_EQ040 = devider4 & Div4 & !_LC4_B16 & !_LC4_B23
# !devider4 & Div4 & _LC4_B16 & !_LC4_B23
# devider4 & !Div4 & _LC4_B16 & !_LC4_B23
# !devider4 & !Div4 & !_LC4_B16 & !_LC4_B23;
-- Node name is ':33'
-- Equation name is '_LC1_B16', type is buried
!_LC1_B16 = _LC1_B16~NOT;
_LC1_B16~NOT = LCELL( _EQ041);
_EQ041 = devider0 & devider1 & devider2 & Div2
# !devider0 & !devider2 & Div2
# !devider1 & !devider2 & Div2
# !devider0 & devider2 & !Div2
# !devider1 & devider2 & !Div2
# devider0 & devider1 & !devider2 & !Div2;
-- Node name is ':65'
-- Equation name is '_LC6_B23', type is buried
_LC6_B23 = DFFE(!_LC6_B23, clk, VCC, VCC, _LC2_B23);
Project Information d:\newvhd\mytest\mainctrl.rpt
** COMPILATION SETTINGS & TIMES **
Processing Menu Commands
------------------------
Design Doctor = off
Logic Synthesis:
Synthesis Type Used = Multi-Level
Default Synthesis Style = NORMAL
Logic option settings in 'NORMAL' style for 'FLEX10K' family
CARRY_CHAIN = ignore
CARRY_CHAIN_LENGTH = 32
CASCADE_CHAIN = ignore
CASCADE_CHAIN_LENGTH = 2
DECOMPOSE_GATES = on
DUPLICATE_LOGIC_EXTRACTION = on
MINIMIZATION = full
MULTI_LEVEL_FACTORING = on
NOT_GATE_PUSH_BACK = on
REDUCE_LOGIC = on
REFACTORIZATION = on
REGISTER_OPTIMIZATION = on
RESYNTHESIZE_NETWORK = on
SLOW_SLEW_RATE = off
SUBFACTOR_EXTRACTION = on
IGNORE_SOFT_BUFFERS = on
USE_LPM_FOR_AHDL_OPERATORS = off
Other logic synthesis settings:
Automatic Global Clock = on
Automatic Global Clear = on
Automatic Global Preset = on
Automatic Global Output Enable = on
Automatic Fast I/O = off
Automatic Register Packing = off
Automatic Open-Drain Pins = on
Automatic Implement in EAB = off
Optimize = 5
Default Timing Specifications: None
Cut All Bidir Feedback Timing Paths = on
Cut All Clear & Preset Timing Paths = on
Ignore Timing Assignments = off
Functional SNF Extractor = off
Linked SNF Extractor = off
Timing SNF Extractor = on
Optimize Timing SNF = off
Generate AHDL TDO File = off
Fitter Settings = NORMAL
Use Quartus Fitter = on
Smart Recompile = off
Total Recompile = off
Interfaces Menu Commands
------------------------
EDIF Netlist Writer = off
Verilog Netlist Writer = off
VHDL Netlist Writer = off
Compilation Times
-----------------
Compiler Netlist Extractor 00:00:00
Database Builder 00:00:01
Logic Synthesizer 00:00:00
Partitioner 00:00:00
Fitter 00:00:01
Timing SNF Extractor 00:00:00
Assembler 00:00:00
-------------------------- --------
Total Time 00:00:02
Memory Allocated
-----------------
Peak memory allocated during compilation = 26,657K
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