modsel.v

来自「本程序功能: DDS文件夹内的程序」· Verilog 代码 · 共 50 行

module ModSel (da1, da2, da3, ModSel,da_out);

input[7:0] da1,da2,da3;
input[1:0]	ModSel;
output[7:0] da_out;


reg[7:0]	da_out;


always
begin
	case (ModSel)
       0:
       begin
               da_out=da1;
       end
       1:
       begin
               da_out=da2;
       end
       2:
       begin
               da_out=da3;
       end
       3:
       begin
               da_out=0;
       end
       default :
       begin
               da_out=0;
       end
	endcase
end


  // Port Declaration

  // Wire Declaration

  // Integer Declaration

  // Concurent Assignment

  // Always Statement

endmodule