mytest.rpt

本程序功能: DDS文件夹内的程序

Code:

s = Synthesized pin or logic cell
+ = Synchronous flipflop
/ = Slow slew-rate output
! = NOT gate push-back
r = Fitter-inserted logic cell
p = Packed register


Device-Specific Information:                     e:\esd_prg\verilog\mytest.rpt
mytest

** FASTTRACK INTERCONNECT UTILIZATION **

Row FastTrack Interconnect:

          Global         Left Half-      Right Half-
         FastTrack       FastTrack       FastTrack 
Row     Interconnect    Interconnect    Interconnect    Input Pins     Output Pins     Bidir Pins
A:      10/ 96( 10%)     9/ 48( 18%)     2/ 48(  4%)    2/16( 12%)      3/16( 18%)     0/16(  0%)
B:      27/ 96( 28%)    18/ 48( 37%)    10/ 48( 20%)    0/16(  0%)      4/16( 25%)     0/16(  0%)
C:      16/ 96( 16%)    18/ 48( 37%)     3/ 48(  6%)    4/16( 25%)      1/16(  6%)     0/16(  0%)


Column FastTrack Interconnect:

         FastTrack                                 
Column  Interconnect    Input Pins     Output Pins     Bidir Pins
01:      2/24(  8%)     0/4(  0%)      2/4( 50%)       0/4(  0%)
02:      2/24(  8%)     0/4(  0%)      1/4( 25%)       0/4(  0%)
03:      1/24(  4%)     1/4( 25%)      0/4(  0%)       0/4(  0%)
04:      3/24( 12%)     0/4(  0%)      0/4(  0%)       0/4(  0%)
05:      1/24(  4%)     1/4( 25%)      0/4(  0%)       0/4(  0%)
06:      0/24(  0%)     0/4(  0%)      0/4(  0%)       0/4(  0%)
07:      3/24( 12%)     0/4(  0%)      0/4(  0%)       0/4(  0%)
08:      4/24( 16%)     0/4(  0%)      0/4(  0%)       0/4(  0%)
09:      1/24(  4%)     0/4(  0%)      0/4(  0%)       0/4(  0%)
10:      0/24(  0%)     0/4(  0%)      0/4(  0%)       0/4(  0%)
11:      2/24(  8%)     0/4(  0%)      0/4(  0%)       0/4(  0%)
12:      3/24( 12%)     1/4( 25%)      0/4(  0%)       0/4(  0%)
13:      1/24(  4%)     1/4( 25%)      0/4(  0%)       0/4(  0%)
14:      1/24(  4%)     0/4(  0%)      0/4(  0%)       0/4(  0%)
15:      2/24(  8%)     0/4(  0%)      1/4( 25%)       0/4(  0%)
16:      1/24(  4%)     0/4(  0%)      1/4( 25%)       0/4(  0%)
17:      1/24(  4%)     0/4(  0%)      1/4( 25%)       0/4(  0%)
18:      3/24( 12%)     0/4(  0%)      1/4( 25%)       0/4(  0%)
19:      1/24(  4%)     0/4(  0%)      1/4( 25%)       0/4(  0%)
20:      1/24(  4%)     0/4(  0%)      1/4( 25%)       0/4(  0%)
21:      1/24(  4%)     0/4(  0%)      1/4( 25%)       0/4(  0%)
22:      1/24(  4%)     1/4( 25%)      0/4(  0%)       0/4(  0%)
23:      1/24(  4%)     1/4( 25%)      0/4(  0%)       0/4(  0%)
24:      3/24( 12%)     2/4( 50%)      0/4(  0%)       0/4(  0%)
EA:      3/24( 12%)     0/4(  0%)      0/4(  0%)       0/4(  0%)


Device-Specific Information:                     e:\esd_prg\verilog\mytest.rpt
mytest

** CLOCK SIGNALS **

Type     Fan-out       Name
INPUT       18         PCS
DFF         17         |mainctrl:45|:65
INPUT       11         clk


Device-Specific Information:                     e:\esd_prg\verilog\mytest.rpt
mytest

** EQUATIONS **

clk      : INPUT;
DC       : INPUT;
Mdata0   : INPUT;
Mdata1   : INPUT;
Mdata2   : INPUT;
Mdata3   : INPUT;
Mdata4   : INPUT;
Mdata5   : INPUT;
Mdata6   : INPUT;
Mdata7   : INPUT;
Mh       : INPUT;
PCS      : INPUT;
row0     : INPUT;
row1     : INPUT;
row2     : INPUT;
row3     : INPUT;

-- Node name is 'col0' 
-- Equation name is 'col0', type is output 
col0     = !_LC1_C3;

-- Node name is 'col1' 
-- Equation name is 'col1', type is output 
col1     = !_LC3_C3;

-- Node name is 'col2' 
-- Equation name is 'col2', type is output 
col2     = !_LC5_C7;

-- Node name is 'col3' 
-- Equation name is 'col3', type is output 
col3     =  _LC7_C3;

-- Node name is 'da_cs' 
-- Equation name is 'da_cs', type is output 
da_cs    =  _LC8_C12;

-- Node name is 'da_out0' 
-- Equation name is 'da_out0', type is output 
da_out0  =  _LC7_B15;

-- Node name is 'da_out1' 
-- Equation name is 'da_out1', type is output 
da_out1  =  _LC1_C22;

-- Node name is 'da_out2' 
-- Equation name is 'da_out2', type is output 
da_out2  =  _LC2_C20;

-- Node name is 'da_out3' 
-- Equation name is 'da_out3', type is output 
da_out3  =  _LC1_C20;

-- Node name is 'da_out4' 
-- Equation name is 'da_out4', type is output 
da_out4  =  _LC4_A17;

-- Node name is 'da_out5' 
-- Equation name is 'da_out5', type is output 
da_out5  =  _LC1_A17;

-- Node name is 'da_out6' 
-- Equation name is 'da_out6', type is output 
da_out6  =  _LC2_B15;

-- Node name is 'da_out7' 
-- Equation name is 'da_out7', type is output 
da_out7  =  _LC1_B15;

-- Node name is 'int0' 
-- Equation name is 'int0', type is output 
int0     =  _LC2_C10;

-- Node name is 'Key0' 
-- Equation name is 'Key0', type is output 
Key0     = TRI(_LC1_C2, !_LC1_C10);

-- Node name is 'Key1' 
-- Equation name is 'Key1', type is output 
Key1     = TRI(_LC6_C2, !_LC1_C10);

-- Node name is 'Key2' 
-- Equation name is 'Key2', type is output 
Key2     = TRI(_LC3_C2, !_LC1_C10);

-- Node name is 'Key3' 
-- Equation name is 'Key3', type is output 
Key3     = TRI(_LC2_C2, !_LC1_C10);

-- Node name is '|CmdCtrl:44|:82' = '|CmdCtrl:44|M0' 
-- Equation name is '_LC3_B13', type is buried 
_LC3_B13 = DFFE( _EQ001, !PCS,  VCC,  VCC,  DC);
  _EQ001 =  _LC3_B13 &  Mh
         #  Mdata0 & !Mh;

-- Node name is '|CmdCtrl:44|:81' = '|CmdCtrl:44|M1' 
-- Equation name is '_LC5_B18', type is buried 
_LC5_B18 = DFFE( _EQ002, !PCS,  VCC,  VCC,  DC);
  _EQ002 =  _LC5_B18 &  Mh
         #  Mdata1 & !Mh;

-- Node name is '|CmdCtrl:44|:80' = '|CmdCtrl:44|M2' 
-- Equation name is '_LC2_B2', type is buried 
_LC2_B2  = DFFE( _EQ003, !PCS,  VCC,  VCC,  DC);
  _EQ003 =  _LC2_B2 &  Mh
         #  Mdata2 & !Mh;

-- Node name is '|CmdCtrl:44|:79' = '|CmdCtrl:44|M3' 
-- Equation name is '_LC4_B18', type is buried 
_LC4_B18 = DFFE( _EQ004, !PCS,  VCC,  VCC,  DC);
  _EQ004 =  _LC4_B18 &  Mh
         #  Mdata3 & !Mh;

-- Node name is '|CmdCtrl:44|:78' = '|CmdCtrl:44|M4' 
-- Equation name is '_LC6_B18', type is buried 
_LC6_B18 = DFFE( _EQ005, !PCS,  VCC,  VCC,  DC);
  _EQ005 =  _LC6_B18 &  Mh
         #  Mdata4 & !Mh;

-- Node name is '|CmdCtrl:44|:77' = '|CmdCtrl:44|M5' 
-- Equation name is '_LC5_B24', type is buried 
_LC5_B24 = DFFE( _EQ006, !PCS,  VCC,  VCC,  DC);
  _EQ006 =  _LC5_B24 &  Mh
         #  Mdata5 & !Mh;

-- Node name is '|CmdCtrl:44|:76' = '|CmdCtrl:44|M6' 
-- Equation name is '_LC8_B24', type is buried 
_LC8_B24 = DFFE( _EQ007, !PCS,  VCC,  VCC,  DC);
  _EQ007 =  _LC8_B24 &  Mh
         #  Mdata6 & !Mh;

-- Node name is '|CmdCtrl:44|:75' = '|CmdCtrl:44|M7' 
-- Equation name is '_LC3_B2', type is buried 
_LC3_B2  = DFFE( _EQ008, !PCS,  VCC,  VCC,  DC);
  _EQ008 =  _LC3_B2 &  Mh
         #  Mdata7 & !Mh;

-- Node name is '|CmdCtrl:44|:74' = '|CmdCtrl:44|M8' 
-- Equation name is '_LC6_B11', type is buried 
_LC6_B11 = DFFE( _EQ009, !PCS,  VCC,  VCC,  DC);
  _EQ009 =  _LC6_B11 & !Mh
         #  Mdata0 &  Mh;

-- Node name is '|CmdCtrl:44|:73' = '|CmdCtrl:44|M9' 
-- Equation name is '_LC5_B11', type is buried 
_LC5_B11 = DFFE( _EQ010, !PCS,  VCC,  VCC,  DC);
  _EQ010 =  _LC5_B11 & !Mh
         #  Mdata1 &  Mh;

-- Node name is '|CmdCtrl:44|:72' = '|CmdCtrl:44|M10' 
-- Equation name is '_LC4_B2', type is buried 
_LC4_B2  = DFFE( _EQ011, !PCS,  VCC,  VCC,  DC);
  _EQ011 =  _LC4_B2 & !Mh
         #  Mdata2 &  Mh;

-- Node name is '|CmdCtrl:44|:113' 
-- Equation name is '_LC8_B18', type is buried 
_LC8_B18 = DFFE( _EQ012, !PCS,  VCC,  VCC,  VCC);
  _EQ012 =  DC &  _LC8_B18
         # !DC &  Mdata1;

-- Node name is '|CmdCtrl:44|:114' 
-- Equation name is '_LC1_B18', type is buried 
_LC1_B18 = DFFE( _EQ013, !PCS,  VCC,  VCC,  VCC);
  _EQ013 =  DC &  _LC1_B18
         # !DC &  Mdata0;

-- Node name is '|CmdCtrl:44|:132' 
-- Equation name is '_LC8_B2', type is buried 
_LC8_B2  = DFFE( _EQ014, !PCS,  VCC,  VCC,  DC);
  _EQ014 =  _LC8_B2 & !Mh
         #  Mdata7 &  Mh;

-- Node name is '|CmdCtrl:44|:133' 
-- Equation name is '_LC5_B2', type is buried 
_LC5_B2  = DFFE( _EQ015, !PCS,  VCC,  VCC,  DC);
  _EQ015 =  _LC5_B2 & !Mh
         #  Mdata6 &  Mh;

-- Node name is '|CmdCtrl:44|:134' 
-- Equation name is '_LC3_B18', type is buried 
_LC3_B18 = DFFE( _EQ016, !PCS,  VCC,  VCC,  DC);
  _EQ016 =  _LC3_B18 & !Mh
         #  Mdata5 &  Mh;

-- Node name is '|CmdCtrl:44|:135' 
-- Equation name is '_LC2_B18', type is buried 
_LC2_B18 = DFFE( _EQ017, !PCS,  VCC,  VCC,  DC);
  _EQ017 =  _LC2_B18 & !Mh
         #  Mdata4 &  Mh;

-- Node name is '|CmdCtrl:44|:136' 
-- Equation name is '_LC7_B18', type is buried 
_LC7_B18 = DFFE( _EQ018, !PCS,  VCC,  VCC,  DC);
  _EQ018 =  _LC7_B18 & !Mh
         #  Mdata3 &  Mh;

-- Node name is '|KBSCAN:2|:16' = '|KBSCAN:2|cnt0' 
-- Equation name is '_LC4_C12', type is buried 
_LC4_C12 = DFFE( _EQ019,  clk,  VCC,  VCC,  VCC);
  _EQ019 =  _LC4_C12 & !_LC7_C12
         # !_LC4_C12 &  _LC7_C12;

-- Node name is '|KBSCAN:2|:15' = '|KBSCAN:2|cnt1' 
-- Equation name is '_LC3_C12', type is buried 
_LC3_C12 = DFFE( _EQ020,  clk,  VCC,  VCC,  VCC);
  _EQ020 =  _LC3_C12 & !_LC4_C12
         # !_LC3_C12 &  _LC4_C12 &  _LC7_C12