📄 modsel.rpt
字号:
FastTrack FastTrack FastTrack
Row Interconnect Interconnect Interconnect Input Pins Output Pins Bidir Pins
A: 6/ 96( 6%) 5/ 48( 10%) 0/ 48( 0%) 6/16( 37%) 3/16( 18%) 0/16( 0%)
B: 8/ 96( 8%) 0/ 48( 0%) 7/ 48( 14%) 6/16( 37%) 3/16( 18%) 0/16( 0%)
C: 0/ 96( 0%) 0/ 48( 0%) 0/ 48( 0%) 0/16( 0%) 0/16( 0%) 0/16( 0%)
Column FastTrack Interconnect:
FastTrack
Column Interconnect Input Pins Output Pins Bidir Pins
01: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
02: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
03: 1/24( 4%) 1/4( 25%) 0/4( 0%) 0/4( 0%)
04: 1/24( 4%) 1/4( 25%) 0/4( 0%) 0/4( 0%)
05: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
06: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
07: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
08: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
09: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
10: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
11: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
12: 1/24( 4%) 0/4( 0%) 1/4( 25%) 0/4( 0%)
13: 1/24( 4%) 0/4( 0%) 1/4( 25%) 0/4( 0%)
14: 1/24( 4%) 1/4( 25%) 0/4( 0%) 0/4( 0%)
15: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
16: 1/24( 4%) 1/4( 25%) 0/4( 0%) 0/4( 0%)
17: 1/24( 4%) 1/4( 25%) 0/4( 0%) 0/4( 0%)
18: 1/24( 4%) 1/4( 25%) 0/4( 0%) 0/4( 0%)
19: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
20: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
21: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
22: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
23: 1/24( 4%) 1/4( 25%) 0/4( 0%) 0/4( 0%)
24: 1/24( 4%) 1/4( 25%) 0/4( 0%) 0/4( 0%)
EA: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
Device-Specific Information: d:\newvhd\mytest\modsel.rpt
modsel
** EQUATIONS **
da10 : INPUT;
da11 : INPUT;
da12 : INPUT;
da13 : INPUT;
da14 : INPUT;
da15 : INPUT;
da16 : INPUT;
da17 : INPUT;
da20 : INPUT;
da21 : INPUT;
da22 : INPUT;
da23 : INPUT;
da24 : INPUT;
da25 : INPUT;
da26 : INPUT;
da27 : INPUT;
da30 : INPUT;
da31 : INPUT;
da32 : INPUT;
da33 : INPUT;
da34 : INPUT;
da35 : INPUT;
da36 : INPUT;
da37 : INPUT;
ModSel0 : INPUT;
ModSel1 : INPUT;
-- Node name is 'da_out0'
-- Equation name is 'da_out0', type is output
da_out0 = _LC1_A12;
-- Node name is 'da_out1'
-- Equation name is 'da_out1', type is output
da_out1 = _LC7_A12;
-- Node name is 'da_out2'
-- Equation name is 'da_out2', type is output
da_out2 = _LC2_A12;
-- Node name is 'da_out3'
-- Equation name is 'da_out3', type is output
da_out3 = _LC8_A12;
-- Node name is 'da_out4'
-- Equation name is 'da_out4', type is output
da_out4 = _LC1_B13;
-- Node name is 'da_out5'
-- Equation name is 'da_out5', type is output
da_out5 = _LC5_B13;
-- Node name is 'da_out6'
-- Equation name is 'da_out6', type is output
da_out6 = _LC3_B13;
-- Node name is 'da_out7'
-- Equation name is 'da_out7', type is output
da_out7 = _LC8_B13;
-- Node name is '~81~1'
-- Equation name is '~81~1', location is LC7_B13, type is buried.
-- synthesized logic cell
_LC7_B13 = LCELL( _EQ001);
_EQ001 = da27 & ModSel0 & !ModSel1
# da37 & !ModSel0 & ModSel1;
-- Node name is ':81'
-- Equation name is '_LC8_B13', type is buried
_LC8_B13 = LCELL( _EQ002);
_EQ002 = _LC7_B13
# da17 & !ModSel0 & !ModSel1;
-- Node name is '~82~1'
-- Equation name is '~82~1', location is LC6_B13, type is buried.
-- synthesized logic cell
_LC6_B13 = LCELL( _EQ003);
_EQ003 = da26 & ModSel0 & !ModSel1
# da36 & !ModSel0 & ModSel1;
-- Node name is ':82'
-- Equation name is '_LC3_B13', type is buried
_LC3_B13 = LCELL( _EQ004);
_EQ004 = _LC6_B13
# da16 & !ModSel0 & !ModSel1;
-- Node name is '~83~1'
-- Equation name is '~83~1', location is LC4_B13, type is buried.
-- synthesized logic cell
_LC4_B13 = LCELL( _EQ005);
_EQ005 = da25 & ModSel0 & !ModSel1
# da35 & !ModSel0 & ModSel1;
-- Node name is ':83'
-- Equation name is '_LC5_B13', type is buried
_LC5_B13 = LCELL( _EQ006);
_EQ006 = _LC4_B13
# da15 & !ModSel0 & !ModSel1;
-- Node name is '~84~1'
-- Equation name is '~84~1', location is LC2_B13, type is buried.
-- synthesized logic cell
_LC2_B13 = LCELL( _EQ007);
_EQ007 = da24 & ModSel0 & !ModSel1
# da34 & !ModSel0 & ModSel1;
-- Node name is ':84'
-- Equation name is '_LC1_B13', type is buried
_LC1_B13 = LCELL( _EQ008);
_EQ008 = _LC2_B13
# da14 & !ModSel0 & !ModSel1;
-- Node name is '~85~1'
-- Equation name is '~85~1', location is LC6_A12, type is buried.
-- synthesized logic cell
_LC6_A12 = LCELL( _EQ009);
_EQ009 = da23 & ModSel0 & !ModSel1
# da33 & !ModSel0 & ModSel1;
-- Node name is ':85'
-- Equation name is '_LC8_A12', type is buried
_LC8_A12 = LCELL( _EQ010);
_EQ010 = _LC6_A12
# da13 & !ModSel0 & !ModSel1;
-- Node name is '~86~1'
-- Equation name is '~86~1', location is LC5_A12, type is buried.
-- synthesized logic cell
_LC5_A12 = LCELL( _EQ011);
_EQ011 = da22 & ModSel0 & !ModSel1
# da32 & !ModSel0 & ModSel1;
-- Node name is ':86'
-- Equation name is '_LC2_A12', type is buried
_LC2_A12 = LCELL( _EQ012);
_EQ012 = _LC5_A12
# da12 & !ModSel0 & !ModSel1;
-- Node name is '~87~1'
-- Equation name is '~87~1', location is LC4_A12, type is buried.
-- synthesized logic cell
_LC4_A12 = LCELL( _EQ013);
_EQ013 = da21 & ModSel0 & !ModSel1
# da31 & !ModSel0 & ModSel1;
-- Node name is ':87'
-- Equation name is '_LC7_A12', type is buried
_LC7_A12 = LCELL( _EQ014);
_EQ014 = _LC4_A12
# da11 & !ModSel0 & !ModSel1;
-- Node name is '~88~1'
-- Equation name is '~88~1', location is LC3_A12, type is buried.
-- synthesized logic cell
_LC3_A12 = LCELL( _EQ015);
_EQ015 = da20 & ModSel0 & !ModSel1
# da30 & !ModSel0 & ModSel1;
-- Node name is ':88'
-- Equation name is '_LC1_A12', type is buried
_LC1_A12 = LCELL( _EQ016);
_EQ016 = _LC3_A12
# da10 & !ModSel0 & !ModSel1;
Project Information d:\newvhd\mytest\modsel.rpt
** COMPILATION SETTINGS & TIMES **
Processing Menu Commands
------------------------
Design Doctor = off
Logic Synthesis:
Synthesis Type Used = Multi-Level
Default Synthesis Style = NORMAL
Logic option settings in 'NORMAL' style for 'FLEX10K' family
CARRY_CHAIN = ignore
CARRY_CHAIN_LENGTH = 32
CASCADE_CHAIN = ignore
CASCADE_CHAIN_LENGTH = 2
DECOMPOSE_GATES = on
DUPLICATE_LOGIC_EXTRACTION = on
MINIMIZATION = full
MULTI_LEVEL_FACTORING = on
NOT_GATE_PUSH_BACK = on
REDUCE_LOGIC = on
REFACTORIZATION = on
REGISTER_OPTIMIZATION = on
RESYNTHESIZE_NETWORK = on
SLOW_SLEW_RATE = off
SUBFACTOR_EXTRACTION = on
IGNORE_SOFT_BUFFERS = on
USE_LPM_FOR_AHDL_OPERATORS = off
Other logic synthesis settings:
Automatic Global Clock = on
Automatic Global Clear = on
Automatic Global Preset = on
Automatic Global Output Enable = on
Automatic Fast I/O = off
Automatic Register Packing = off
Automatic Open-Drain Pins = on
Automatic Implement in EAB = off
Optimize = 5
Default Timing Specifications: None
Cut All Bidir Feedback Timing Paths = on
Cut All Clear & Preset Timing Paths = on
Ignore Timing Assignments = off
Functional SNF Extractor = off
Linked SNF Extractor = off
Timing SNF Extractor = on
Optimize Timing SNF = off
Generate AHDL TDO File = off
Fitter Settings = NORMAL
Use Quartus Fitter = on
Smart Recompile = off
Total Recompile = off
Interfaces Menu Commands
------------------------
EDIF Netlist Writer = off
Verilog Netlist Writer = off
VHDL Netlist Writer = off
Compilation Times
-----------------
Compiler Netlist Extractor 00:00:00
Database Builder 00:00:00
Logic Synthesizer 00:00:00
Partitioner 00:00:01
Fitter 00:00:02
Timing SNF Extractor 00:00:00
Assembler 00:00:00
-------------------------- --------
Total Time 00:00:03
Memory Allocated
-----------------
Peak memory allocated during compilation = 13,929K
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